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OCP-IP Governing Steering Committee Meeting Mountain View, California August 23, 2007

OCP-IP Governing Steering Committee Meeting Mountain View, California August 23, 2007.

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OCP-IP Governing Steering Committee Meeting Mountain View, California August 23, 2007

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  1. OCP-IPGoverning Steering Committee MeetingMountain View, CaliforniaAugust 23, 2007

  2. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene - Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  3. Call to Order and Agenda Review (Ian) • Call to Order • Welcome from the President • Review Agenda • Any additional items? • Vote to approve last GSC Meeting Minutes • 23rd GSC Meeting, 20 April 2007, Nice, France • Miscellaneous Items: • Recognize electronic votes that upgraded “HDL Dynamics” and “pls Development Tools” • DWG chair arrangement: Bob U. temporarily individual contributor

  4. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair 8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM:System Level Design WG (Mark)- Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene- Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  5. 1:00- 1:20 PM: Technical Vision WG Status / Restated (Ian) 1:20- 1:40 PM: Progress in Asia and VSIA Issue (Ian) 1:40- 2:00 PM: Japan Recruiting Plan (Nakada-san)2:00- 2:15 PM: 2007 Goals 2:15- 3:00 PM: AI Review (Ian) - ARM Discussion - DesignWare and CoreCreator Updates 3:00- 3:15 PM: 2007 Budget (Ian)3:15- 3:30 PM: PR Update (Joe) 3:30- 3:45 PM: Recruiting Update (Joe) 3:45- 4:00 PM: Motion to Adjourn/ Break/ Reconvene 4:00- 4:15 PM: Administrative Update (VTM) 4:15- 4:20 PM: Enabling Resolution4:20- 4:30 PM: Collateral Review (VTM)4:30 PM: Motion to Adjourn

  6. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene-Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  7. Next GSC Meeting (Ian) • 25th GSC Meeting • Mid – Late November? • Preferences for Location? • Reminder: Next GSC meeting is an annual meeting (budgets, etc., with TVWG strategic planning in January as usual)

  8. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian)8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene-Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  9. SLD WG Update Mark Burton (Greensocs), August 2007

  10. Overview • Overview Status for SLD • Results of “Experiment” • Goals from TVWG • Mid-term - unchanged.

  11. System Level Design WG Status (Mark) • 2.2.1 minor revision release STILL ongoing • Really small changes • Much later than expected • Some minor bugs in adapters package being handled • Resource limited (CoWare providing much of the effort) • Will represent only small delta’s on the 2.2 • Now expected September

  12. Activity Status for TVWG

  13. The SLD Mid-Term Vision - unchanged • OUR KIT IS HIGH QUALITY, AND STABLE. • Ensure that OCP users have a 'complete' modelling infrastructure available • multiple levels of abstraction (pure-functional to cycle-accurate) and use models (software development, architecture exploration, etc) • completeness means • bus interface , performance monitoring interface ,system debug interface and configuration interface • Make this modelling infrastructure standards compliant. • E.g. drive existing OCP-IP experience and expertise into OSCI-TLM • Maintain alignment between OSCI-TLM OCP-IP

  14. SLD WGBackup Next Generation OCP-IP TLM Feasibility Study

  15. TRANSACTION level modelling experiment Request and Response level modelling with a complex channel Transaction level model with no channel My IP His IP My IP His IP Her IP Your IP OCP Channel Request … Response Transaction sharedlinked to all interface calls COMPLEX interface. Must control the state machine in the channel SIMPLE interface, passes transaction to next blockfor processing. (Transaction may be passed backwards and forwards in accordancewith protocol) Protocol is KEY State machines modelled INSIDE IP blocks (optionally in library code) No top level instantiation of channels between IP

  16. Results main points • Significant reduction in user code complexity • Slight increase is speed at all abstraction levels • Significant increase in speed for NoC designs • Backwards compatibility is achievable • Highly aligned with work in OSCI’s TLM WG • Now we have a LOT of work to do - build this to the quality of the current SLD kit which has had many man years of effort. • MINIMUM 6-8 man months to have basic kit available (co-ordinated with OSCI release) • Man years to get to the quality we would like.

  17. OCP-IP and OSCI-TLM Technology Alignment Roadmap Proposal for OCP-IP SLD Working Group James Aldis (TI) and Mark Burton (Greensocs), May 2007

  18. Long Term Vision • TL4 (programmer’s view) • OCP is irrelevant as models use a ‘generic’ memory-mapped bus interface optimised for speed • This comes from OSCI. • TL3 (programmer’s view with coarse timing) • Same as TL4, it comes from OSCI . • OCP-IP provides guidelines on OCP sockets • TL2 (timing approximate) • OCP-specific handshaking and flow control must be modeled • OSCI provides a generic ‘cycle-approx bus modelling framework’ and OCP-IP maintains an OCP personality for this • TL1 (timing accurate) • OCP-specific handshaking and flow control must be modeled • OSCI provides a generic ‘cycle-accurate bus modelling framework’ and OCP-IP maintains an OCP personality for this

  19. Where is OSCI now? • Plans to release TLM-2.0 before end of 2007 • TLM-2.0 may contain only TL4 • TLM-2.0 might contain TL3 as well, but looks unlikely before TLM-2.1 • Will not contain TL2 or TL1 • TL1 is likely to be on OSCI’s roadmap • Strong pressure inside the OSCI WG to move away from pass-by-value to • Single transaction • Pass by pointer

  20. Where is OCP-IP SLD now? • Have stable TL1, TL2 and TL3 • Code has reached usage/age it needs updating to ensure ease-of-maintenance. • Simulation speed could be improved • Uses mainly pass-by-value/split req/resp • ie risk of substantial inefficiency bridging to OSCI-TLM • After several years of being a “competitive advantage” for OCP, our SLD infrastructure could soon be out-of-date

  21. Technical Proposal • Create an alternative OCP-IP-TL1 technology • Faster than current • Cleaner than current • Aligned with where OSCI-TLM is likely to go • Can be used for TL2 with same acceleration as today but much less functional difference (just fewer calls to the same API) • Possible to provide support for existing OCP-TL1/TL2 modules • OCP-IP drives this into OSCI-TLM • Document how to use OSCI-TLM for OCP-TL3 and OCP-TL4

  22. Resourcing Proposal • TI/Greensocs have completed a proof-of-concept for a replacement OCP-TL1 • But replacing the entire TL1 infrastructure needs • Some significant investment • A “lead organisation” to ensure consistency and quality • We don’t believe it can be done with voluntary contributions only • Propose that OCP-IP members pay Greensocs to do it • Cost might be ~80k Euro for one-off contract • To be confirmed • Propose splitting this cost between the four OCP-IP GSC members, CoWare and OCP-IP • Relatively low cost to each • OCP-IP contribution represents “the commitment of the broad OCP community”

  23. Supporters of this proposal • We have discussed this document with the following companies (immediately below) • Without exception, all have reacted positively on the technical side, without making any formal commitment of any kind. • We have not CONFIRMED financial support yet • Texas Instruments • Nokia • Sonics • CoWare • Toshiba

  24. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene-Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  25. Functional Verification WG Status (Steve) • Performance Standard • Initiated FVWG discussions in January, participated in discussions with other WG in early February • Expected completion: End September 2007 • Expected phases • Agreement on basic concepts (completed) • List of important events, measurements, etc. (review copy completed) • Structural document, including lists, charts, etc. (review copy completed) • Formatting by Technical Writer, end August (on hold) • FVWG review, end September (on hold) • Good news: Review copy, focused on critical events and delays (need to add throughput), released for review • Bad news: Only 1 FVWG member (Ravi@Sonics) has provided review input, no Spec’n WG review input • Protocol Compliance Clarification • General review and cleanup, etc., of the compliance sections • Expected completion: End September 2007 • Expected phases • Detailed review of ‘Compliance section’, end February • Detailed review of ‘Protocol Compliance Checks’, end April • Detailed review of ‘Configuration Compliance Checks’, end June • Detailed review of ‘Functional Coverage’, end August • Modifications completed by Technical Writer, end September • Bad news: WG members not providing any input • Good news: No good news to report on this one

  26. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene-Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  27. OCP-IP Standard Debug Signals for IP-Blocks GSC Status Aug 23, 2007 Bob Uvacek Neal Stollon

  28. 4 5 6 7 8 9 10 11 12 1 April-June Work on a textmatching the OCP-Standard April-June Publish articles, advertise, build opinion April-June (Synchronize result with other groups proposals) June-Aug Make reviews with all OCP Debug Reviewers September Propose it as standard September Publish it inside OCP for greater review September Have maybe example in RTL, C++, XML December Release On-chip Debug-HW Signaling Standard 2007 on the OCP public website OCP-IP Debug Interface Standard Roadmap

  29. Debug WG Status Aug 07 • Made strawman of OCP Standard 3. with Debug • Writing simplified text of standard  TI review • OCP Document format (first united with and then separated from OCP 2.2) • Preparing Debug Example • ITRI Donations • PLS Donations • Infineon Intentions (SPRINT publish in OCP?) • Outlook

  30. OCP Debug Document Structure • Continue the OCP Interface Standard 2.2 text with a Debug Part • Make independent Annexes (Extensions) to The OCP Interface Standard 2.2 • Possible additional parts for a complete Debug Standardization • OCP Debug Socket Signals (our present work, yellow, OCP-IP) • DAS-API and Register Interface (as shown green in SLD, SPRINT) • JTAG and TRACE pin interface (as shown in pink, MIPI) • HW Debug Interface for EDA HW Debuggers (over JTAG, ITRI) • SLD Debug Channel abstraction and modeling in C++ (OSCI) • Because of the many possible Extensions variant 2) seems more appropriate. The GSC has voted on this. ____________________________________________________________ • Result: First make it independent then unite it with current version of OCP Spec

  31. ITRI-Donations • 2007 • Module Debug API (Debug registers) • DB API (ESL in question; HW-DB out of reach) • OCP Debug Seminar at year end • 2008 • Device/ICE API • Debugger API • OCP Seminar

  32. SW Level Debug Debugger API Virtual Level Debug IP-XACT Soft Trace DB API Module Debug API OCP - XML Interfaces Trace Inference OCP - C++ Models Device/ICE API Device Level Debug Hard Trace OCP - RTL IPs ITRI-Working Items

  33. Not Defined Yet PLS Donations OCP Bus & Sockets MASTER SLAVE DEBUG HW-level Debug SW-level Debug S M D D S M D D S M D D S D SLD Virtual SoC Assertion DSP RISC IP MEM Simulation HW Debuggers FSDB Reader BusObsrv CrossTr Trace JTAG Soft Trace FSDB FSDB Writer JTAG DFT SCAN SW Debuggers C++ Channels CrossTr XML IP-XACT XML RISC M JTAG Embedded SW S XML Inference ? IP Assertion MEM JTAG TRACE BOX FSDB Reader Trace DSP D Hard Trace FSDB BusObsrv FSDB Writer RTL Physical SoC JTAG BOX SoC Debug Example - OCP

  34. PLS Donations DIF and DAS 2 Additional Helper Interfaces can be offered: Registers for SW and JTAG for HW community JTAG

  35. The OCP Debug Standard would make this activity obsolete!

  36. Outlook • Send out the standard text to OCP members for review in August • Cover the Debug Example items by the WG members: • Two cores and OCP-Fabric, ITRI • Debug system MCDS, Infineon • Debugger software, PLS • Open is: • Crosstrigger, OCP-Bus-observer, OCP-Wrappers • Debug Register definitions • ESL models of all items

  37. OCP-IP Debug Interface Standard Group • Contractor (Ex. Toshiba) Bob Uvacek, chair • HDL Dynamics (Ex. MIPS/FS2) Neal Stollon • TI Gilbert Laurenti • Toshiba CY Pei • OCP-IP contacts Jeff Phillips, Brian Sage, Ian Mackintosh Reviewing members • Nexus Neal Stollon, TBD • Sonics Stefan Goette, review standard, look at integration with OCP • Cadence Mike Young, Ran Avinun • MIPI Rolf Kuehnis, Gary Swoboda • ITRI/Springsoft Alan Su, (Dr. Lee) • SPIRIT Neal Stollon, (Debug-WG Chair Anthony Berent, ARM) • PLS Jens Braunes • Infineon Albrecht Mayer

  38. RTL Hardware IP OCP-IP Debug Interface Standard C++ Models XML Interfaces OSCI SPIRIT 1) Reach that MIPS-Debug-HW could connect to ARM-core and opposite 2) Reach that Debug-Signals connect/plug to the System-Bus through Sockets 3) Reach that all IP-blocks, not just cores, can connect to the debug system 4) Reach that Debug-HW and DFT-HW “share” as much as possible OCP-IP Debug Interface Standard Goals

  39. OCP Debug Signals Options (Debug Socket) Baseline Debug Socket Signals • 1149.1 JTAG - TCK, TMS, TDI, TDO - part of OCP 2.1 spec • Debug_reset, debug_reset_en • MReqDebug, Msuspend, DebugSerror, DebugCon, • NoSResp, ForceResp, ForceAbort, ForceAbortAck Functional Specific Options • Cross Trigger Interfaces : Trigger_in_condition[n:0], Trigger_out_Action[n:0], Trigger_out_enable[n:0], Ext_trig _clk, Ext _condition[n:0], Ext _action[n:0] • Trace/Debug Synchronization : SyncRunSyncRunAck • Trace TraceTrigger[x] • TimeStamp Interfaces ts_clk ts_reset Target Application Specific Options • Power Management : PWRDomainStatus, CLKDomainStatus Extended response field [2:0] – No Power, No Clk • Security : MReqSecure, DebugMode[1:0] , TraceMode[1:0], TAPenable

  40. OCP Debug Example Plan - 8/17/07 RTLESL • Debug Server ----- ----- • Debugger SW PLS PLS • Debug system MCDS MCDS • OCP wrap Debug Who? --- • OCP Fabric Sonics OCP • Core 1 ARM ARM • Core 2 Infineon Infineon • Memory Model ? ? • Simulator Cadence CoWare • Location/Owner SPRINT ITRI

  41. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene-Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  42. NoC Benchmarking WG Update (Cristian) • Activities within the NoCBWG • Panel on NoC benchmarks at the IEEE NoC Symposium, May 2007 • On-going work for defining benchmarks formats: • NoC hardware description • Application modeling • Micro-benchmarks • Start circulating the first draft in Sept. 07 • Feedback on benchmarks format and test cases from industry members expected soon after

  43. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene-Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  44. Break

  45. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew)- Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene-Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  46. SWG Update Placeholder

  47. 8:15- 8:30 AM: Coffee Available8:30- 8:40 AM: Call to Order, Introductions, Agenda Review, Last Minutes (Ian) - Recognition of Electronic GSC Votes (HDL, PLS) - Temporary Arrangement for Debug WG Chair8:40- 8:45 AM: Next GSC Meeting (Ian) 8:45- 9:30 AM: System Level Design WG (Mark) - Include future TLM kit development discussion (James)9:30- 10:00 AM: Functional Verification WG (Steve)10:00-10:45 AM: Debug WG (Bob)10:45-11:15 AM: NoC BWG Update (Cristian)11:15-11:30 AM: Motion to Adjourn/ Break/ Reconvene11:30-12:00 PM: Specification WG Status (Drew) - Cache Coherence SG Status (Drew) - Next OCP Specification Version and Release Date (Drew)12:00-1:00 PM: Motion to Adjourn/ Lunch/ Reconvene - Lunch Discussion: XML schema.conf files - Record AIs after reconvene if applicable

  48. Lunch

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