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XC9500XL New 3.3v ISP CPLDs

XC9500XL New 3.3v ISP CPLDs. XC9500XL Key Features. High performance t PD = 4ns, f SYS = 200MHz 36 to 288 macrocell densities Highest programming reliability 10,000 program/erase cycles Most complete IEEE 1149.1 JTAG support Space-efficient packaging, including c hip s cale p kg

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XC9500XL New 3.3v ISP CPLDs

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  1. XC9500XLNew 3.3v ISP CPLDs

  2. XC9500XL Key Features • High performance • tPD = 4ns, fSYS = 200MHz • 36 to 288 macrocell densities • Highest programming reliability • 10,000 program/erase cycles • Most complete IEEE 1149.1 JTAG support • Space-efficient packaging, including chip scale pkg • Industry’s first 0.35um Flash CPLD

  3. Advanced, 2nd Generation Pin-Locking Superior routability with speed Maximum Flexibility 54-input function block fan-in 90 p-terms per output 3 global, locally invertible clocks global set/reset pin p-term OE per macrocell clock enable XC9500XL Architecture Embraces In-System Changes

  4. XC9500XL System Features • I/O Flexibility • 5v tolerant; direct interface to 3.3v & 2.5v • Input hysteresis on all pins • User programmable grounds • Bus hold circuitry for simple bus interface • Easy ATE integration for ISP & JTAG • fast, concurrent programming times

  5. New XC9500XL 3.3V Family XC9536XL XC9572XL XC95144XL XC95288XL 288 Macrocells 36 72 144 6400 Usable Gates 800 1600 3200 tPD (ns) 4 5 5 6 200 178 178 151 fSYSTEM Packages (Max. User I/Os) 44PC (34) 64VQ (36) 48CS (36) 44PC (34) 64VQ(52) 100TQ (72) 48CS (38) 100TQ (81) 144TQ (117) 144CS (117) 144TQ (117) 208PQ (168) 352BG (192) BGA CSP

  6. Most Complete JTAG Testability • IEEE Std 1149.1 boundary-scan • testability & advanced system debug/diagnosis • 8 instructions supported (incl. CLAMP) • Full support on all family members • Industry-standard ISP interface • Complete 3rd party support

  7. Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer New 48-pin CSP: 1/3 size of the VQ44 Uses standard IR techniques for mounting to PC board

  8. Simplified Project Management Implementation Templates for Speed & Density Push Button Design Flows USER BENEFITS Faster Clock Speeds Higher Device Utilization optimized logic/cm2 Industry’s Best Pin-Locking more design flexibility, less risk, lower cost Productive Implementation Flow for CPLDs

  9. Xilinx Lowering Cost Across The Supply Chain LEADING EDGE TECHNOLOGY “MEMORY STYLE” MANUFACTURING STREAM-LINED OPERATIONS • 1st with Flash ISP • Only true 0.35um • Apply memory R&D advantages to CPLDs • Long-term foundry agreements • Stream-lined device/pkg offerings • High volume packages • 10ns slowest speed grade • Off-shore sort, test and assembly • Multi-site parallel test • Fast time-to-market

  10. XC9500XLThe Complete CPLD Solution • Product Life Cycle Support • Flexible 3.3v ISP Architecture • New Leadership Features • Productive Software • Lowest Cost Solution

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