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TOTFED – Firmware (1). Firmware: - 3 different ALTERA FPGA’s Cyclone Stratix Stratix II GX - up to now 4 different FPGA’s designs: “VME64x Controller” “MAIN Controller” 1 to 3 “MERGER Controller” “OptoRX Controller” – see Michele slides. TOTFED – Firmware (2).
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TOTFED – Firmware (1) Firmware: - 3 different ALTERA FPGA’s Cyclone Stratix Stratix II GX - up to now 4 different FPGA’s designs: “VME64x Controller” “MAIN Controller” 1 to 3 “MERGER Controller” “OptoRX Controller” – see Michele slides
TOTFED – Firmware (2) • “VME64x Controller” - Version 07 on SVN • - VME Main Controller • - VME64x complaint device • - Primary Local Bus Controller • - 32bit Data, 20 bit Address and Control • - Secondary Local Bus Controller • - 32bit Data/Address Multiplexed and Control • - used for optional MFEC module • - FPGAs Page Reload interface • - JTAG Controller • - From VME64 bus for remote programming • - Trigger Timing Control (TTC) interface • - Trigger Throttling System (TTS) interface • - I2C Interface for TTCrx chip control – need programming • - Board ID • - Temperatures
TOTFED – Firmware (2) • “MAIN Controller” 1 to 3 - Version 07 on SVN • “MERGER Controller” - Version 07 under test • - INPUT SPY Buffer • - Parallel 192 bit @ 40 MHz SPY Data Buffer • - 6 x 32bit FIFOs for VME readout (or 12 x 16bit) • - MEMORY Interface Controller • - Flow-Through SRAM 18-Mbit (512K x 36) • - 3 chips for 96bit Data @ 80MHz • - Firmware Version • - Local Bus Interface • - 32bit Data, 20 bit Address and Control • - USB 2.0 Interface controller • - High-Speed USB Interface Device CY7C68001 chip - enumeration only • - Interconnect Bus • - 64 bit between every MAIN Controller and MERGER Controller • - Trigger Throttling System (TTS) interface • - S-Link64 Interface Controller (for MERGER only) • - 64bit Parallel Data Bus and Control on P2 connector • - Interface to OptoRX12 – for MAIN only • - 16bit Data, 20 bit Address and Control