1 / 20

LWG2 Power Sequence Introduce

LWG2 Power Sequence Introduce. Prepared By: Withy He. BT+. MOS. DCBATOUT. S5. AD+. MOS. U4. 5V_AUX_S5. U 5. 3D3V_AUX_S5. KBC. EC_PWRBTN#. EN1_5. U45 POK. 5V_S5 3D3V_S5. S5_EN. EN2_3D3. ICH7-M. S3. 1D8V_S3. U44. PM_SLP_S5#. U74. DDR_VREF_S3. S0. PM_SLP_S3#. 5V_S0

jeremy-brown
Download Presentation

LWG2 Power Sequence Introduce

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. LWG2 Power Sequence Introduce Prepared By: Withy He

  2. BT+ MOS DCBATOUT S5 AD+ MOS U4 5V_AUX_S5 U5 3D3V_AUX_S5 KBC EC_PWRBTN# EN1_5 U45 POK 5V_S5 3D3V_S5 S5_EN EN2_3D3 ICH7-M S3 1D8V_S3 U44 PM_SLP_S5# U74 DDR_VREF_S3 S0 PM_SLP_S3# 5V_S0 3D3V_S0 1D8V_S0 U51 U52 U27 U6 2D5V_S0 U74 DDR_VREF_S0 U44 POK 1D05V_S0 U22 POK 1D5V_S0 U25 CPUCORE_ON VCC_CORE_S0 DC-DC Source

  3. DCBATOUT AD+ ACIN ACOK MODE PKPRES# MAX8725 VCTL ICTL DCBATOUT SW BT+ Charge Circuit CONTROL FEEDBACK BATA_IN# KBC CHG_V_PWM CHG_I_PWN DHI DLO CSIP CSIN Charger Circuit

  4. Adapter In AD+ DCBATOUT LP2951 5V_AUX_S5 3D3V_AUX_S5 G913 MOS KBC RE144B MOS H8_RESET# ICH BT+ RTC_AUX_S5 MOS ICH KBCRE144B EC_PWRBTN# PWRBTN#_ICH TPS51120 S5_EN 5V_S5 3D3V_S5 RSMRST#_TO_KBC SB_RSMRST# Power On/Reset Step 1.Adapter In: 2.Power On:

  5. ICH PM_SLP_S5# 1D8V_S3 TPS51124 DDR_VREF_S3 TPS51100 PM_SLP_S3# DDR_VREF_S0 ICH TPS51100 5V_S0 MOS 3D3V_S0 MOS 2D5V_S0 APL5332KAC 1D8V_S0 MOS 1D5V_S0 APL5912_KAC 1D05V_S0 TPS51124 3.S3: 4.S0:

  6. TPS51120 POK CPUCORE_ON VCC_CORE_S0 ISL6262 TPS51124 POK APL5912_KAC POK HCPURST# MCH Calistoga PWROK RSTIN# H_CPURST# RESET# CPU Yonah PWRGOOD CLK GEN VTT_PWRGD# H_PWRGD CLK_EN# ISL6262 PGOOD CPUPWRGD VRMPWRGD ICH PWROK PLTRST1# PCIRST# HDD/CDROM VGATE_PWRGD KBC DEBUG G.F. GPU PWROK RESET# G792 PLT_RST1# LAN PCIRST1# TI PCI 7412 Power SW 5.VCC_CORE_S0: 6.System Reset:

  7. Power On/Reset Sequence

More Related