CMOS Fabrication: Silicon Preparation, Crystal Growth, Wafering, Oxidation, Diffusion, Ion Implantation, Deposition, Met

1. Section 4Fabrication and Layout

2. Fabrication- CMOS Process The Starting Material Preparation 1. Produce Metallurgical Grade Silicon (MGS) SiO2 (sand) + C in Arc Furnace Si- liquid 98% pure 2. Produce Electronic Grade Silicon (EGS) HCl + Si (MGS) Successive purification by distillation Chemical Vapor Deposition (CVD)

3. Fabrication: Crystal Growth • Czochralski Method • Basic idea: dip seed crystal into liquid pool • Slowly pull out at a rate of 0.5mm/min • controlled amount of impurities added to melt • Speed of rotation and pulling rate determine diameter of the ingot • Ingot- 1to 2 meter long • Diameter: 4”, 6”, 8”

4. Fabrication: Wafering • Finish ingot to precise diameter • Mill “ flats” • Cut wafers by diamond saw: Typical thickness 0.5mm • Polish to give optically flat surface

5. Fabrication: Oxidation Quartz Tube O or Water 2 Pump Wafers Vapor Quartz Carrier Resistance Heater • Silicon Dioxide has several uses: - mask against implant or diffusion - device isolation - gate oxide - isolation between layers • SiO2 could be thermally generated • or through CVD • Oxidation consumes silicon • Wet or dry oxidation

6. Fabrication: Diffusion Temp: 1000 • Simultaneous creation of p-n junction over the entire surface of wafer • Doesn’t offer precise control • Good for heavy doping, deep junctions • Two steps: • Pre-deposition • Dopant mixed with inert gas introduced in to a furnace at 1000 oC. • Atoms diffuse in a thin layer of Si surface • Drive-in • Wafers heated without dopant wafers Dopant Gas Resistance Heater

7. Fabrication: Ion Implantation • Precise control of dopant • Good for shallow junctions and threshold adjust • Dopant gas ionized and accelerated • Ions strike silicon surface at high speed • Depth of lodging is determined by accelerating field

8. Fabrication: Deposition Loader 0.1 -1 Torr Pump • Used to form thin film of Polysilicon, Silicon dioxide, Silicon Nitride, Al. • Applications: Polysilicon, interlayer oxide, LOCOS, metal. • Common technique: Low Pressure Chemical Vapor Deposition (CVD). • SiO2 and Polysilicon deposition at 300 to 1000 oC. • Aluminum deposition at lower temperature- different technique Reactant

9. Fabrication: Metallization • Standard material is Aluminum • Low contact resistance to p-type and n-type • When deposited on SiO2, Al2O3 is formed: good adhesive • All wafer covered with Al • Deposition techniques: Vacuum Evaporation Electron Beam Evaporation RF Sputtering • Other materials used in conjunction with or replacement to Al

10. Fabrication: Etching • Wet Etching • Etchants: hydrofluoric acid (HF), mixture of nitric acid and HF • Good selectivity • Problem: • - under cut • - acid waste disposal • Dry Etching • Physical bombardment with atoms or ions • good for small geometries. • Various types exists such as: • Planar Plasma Etching • Reactive Ion Etching Plasma Reactive species RF

11. Fabrication: Lithography • Mask making • Most critical part of lithography is conversion from layout to master mask • Masking plate has opaque geometrical shapes corresponding to the area on the wafer surface where certain photochemical reactions have to be prevented or taken place. • Masks uses photographic emulsion or hard surface • Two types: dark field or clear field • Maskmaking: optical or e-beam

12. Lithography: Mask making Optical Mask Technique 1. Prepare Reticle Use projection like system: -Precise movable stage -Aperture of precisely rectangular size and angular orientation -Computer controlled UV light source directed to photographic plate After flashing, plate is developed yielding reticle

13. Fabrication: Lithography Step & Repeat Printing Printing

14. Lithography: Mask making • Electron Beam Technique • Main problem with optical technique: light diffraction • System resembles a scanning electron microscope + beam blanking and computer controlled deflection

15. Patterning/ Printing • Process of transferring mask features to surface of the silicon • wafer. • Optical or Electron-beam • Photo-resist material (negative or positive):synthetic rubber or • polymer upon exposure to light becomes insoluble ( negative ) • or volatile (positive) • Developer: typically organic solvant-e.g. Xylen • A common step in many processes is the creation and selective • removal of Silicon Dioxide

16. Patterning: Pwell mask

17. Patterning/ Printing SiO2 substrate

18. Fabrication Steps Inspect, measure Post bake Etch Develop, rinse, dry Strip resist mask Printer align expose Deposit or grow layer Pre-bake Apply PR

19. Fabrication Steps

20. VDD Fabrication Steps: P-well Process Diffusion P+ P+ Vin Vo P well p+ n+ n+ p+ p+ p+ n+ n+ P well Substrate n-type

21. Fabrication Steps: P-well Process VDD Diffusion P+ P+ Vin Vo P well p+ n+ n+ p+ p+ p+ n+ n+ P well Substrate n-type

22. Fabrication Steps n+ n+ p+ p+ P well n+ n+ p+ p+ P well Substrate n-type

23. Fabrication Steps Oxidation oxide Substrate n-type Patterning of P-well mask Substrate n-type

24. Fabrication Steps Diffusion: p dopant, Removal of Oxide P-well Si3N4 Deposit Silicon Nitride P-well

25. Fabrication Steps Patterning: Diffusion (active) mask P-well substrate FOX FOX FOX Oxidation substrate

26. Fabrication Steps Thin oxide FOX FOX FOX Remove Si3N4 Grow thin oxide P-well Deposit polysilicon P-well

27. Fabrication Steps Patterning of Polysilicon Poly gates FOX FOX FOX P -well substrate

28. Fabrication Steps P+ Layers and n+ Layer in the Layout p+ layer polysilicon n+ layer P well

29. Fabrication Steps Formation of n+ and p+ Diffusion Areas: N+ Diffusion: - Covering with photo-resist - Patterning of the n+ layer - Diffusion: n+ dopant PR FOX FOX FOX P-well n+ dopant

30. Fabrication Steps Formation of n+ and p+ Diffusion Areas: P+ Diffusion: - Cover with photo-resist - Patterning of the n+ layer - Diffusion: p+ dopant PR n+ n+ P-well P+ dopant n+ n+ p+ p+ P-well

31. Fabrication Steps p+ layer polysilcon metal n+ layer contact P well

32. Fabrication Steps SiO2 Strip PR and Deposit Oxide FOX FOX FOX P-well Substrate Patterning of Contact Mask contact n+ n+ p+ p+ P-well Substrate

33. Fabrication Steps Deposit metal layer Patterning of metal layer Passivation FOX FOX P-well Substrate Deposit Passivation layer

34. CMOS: 3D Structure n+ n+ FOX FOX p+ p+ FOX P-well Substrate (n-type)

35. VDD S G B MP D Vin Vout D (p-well) G B MN S GND The Bulk Contacts VDD n+ layer p+ layer polysilicon (substrate) metal n+ layer contact p+ layer P well Note: Butting contacts provide more efficient area utilization GND

36. N-Well CMOS n+ layer p+ layer metal N-well n+ layer contact p+ layer

37. Twin Tub/Double Layer Metal CMOS Passivation metal II Via Via SiO2 Metal I Metal II FOX n-wel l p-well Substrate P well

38. Layout Design Rules • Specifies geometrical constrains on the layout art work • Dictated by electrical and reliability constraints with the capability of fabrication technology • Addresses two issues: • reproduction of features on silicon • interaction between layers • Main approaches to describe rules: •  based (scalability) • absolute width spacing overlap extension spacing

39.  Based CMOS Design Rules : N Well Process A. N-well  A.1 Minimum size 10 A.2 Minimum spacing 6 (Same potential) A.3 Minimum spacing 8 (Different potentials) B. Active (Diffusion) B.1 Minimum size 3 B.2 Minimum spacing 3 B.3 N-well overlap of p+ 5 B.4 N-well overlap of n+ 3 B.5 N-well space to n+ 5 B.6 N-well space to p+ 3 B3=5 n+ B4=3 p+ B5=5 n+ N-well B6=3 B1=3 p+ p+ B2=3

40.  Based CMOS Design Rules C3=1 C PolyI C.1 Minimum size 2 C.2 Minimum spacing 2 C.3. Spacing to Active 1 C.4. Gate extension 2 D. p-plus/n-plus D.1 Minimum overlap of Active 2 D.2 Minimum size 7 D.3 Minimum overlap of Active 1 in abutting contact D.4. Spacing of p-plus/n-plus to 3 n+/p+ gate C4=2 C2=2 C1=2 D2=7 D2=7 active active p-plus n-plus D1=2

41.  Based CMOS Design Rules E4=2 E3=2 E. Contact E.1 Minimum size 2 E.2 Minimum spacing (Poly) 2 E.3 Minimum spacing (Active) 2 E.4 Minimum overlap Active) 2 E.5 Minimum overlap of Poly 2 E.6 Minimum overlap of Metal 1 E.7 Minimum spacing to Gate 2 F. Metal 1 F.1 Minimum size 3 F.2 Minimum spacing 3 G. Via G.1 Minimum size 3 G.2 Minimum spacing 3 G.3 Minimum Metal I overlap 1 G.4 Minimum Metal II overlap 1 E1=2 F2=3 E6=1 F1=3 Metal I E5=2 H1=3 Metal II G2=3 H2=4 G3,G4=1

42.  Based CMOS Design Rules H. Metal II H.1 Minimum size 3 H.2 Minimum spacing 4 I. Via2 I.1 Minimum size 2 I.2. Minimum spacing 3 J. Metal III J.1 Minimum size 8 J.2. Minimum spacing 5 J.3 Minimum Metal II overlap 2 K. Passivation K.1 Minimum opening 100m K.2 Minimum spacing 150m

43. Layout of a CMOS Inverter Based Design Rules N-well C1 B3 p-plus B4 n-plus E6 Active Via Metal II G1 p-plus n-plus E4 D1 metalI C4

44. Stick Diagram Notation • It helps to visualize the function as well as topology • It helps in floor planning • 4 layers for SLM: Poly, diffusion, metal, contact • 6 layers for DLM: Poly, Diffusion, Metal I, Metal II, Contact, Via • Construction Guidelines: • When two wires of the same color intersects or touch, they are electrically connected. • Contacts represented by (X) and via by ( ) • When poly crosses diffusion, a transistor is formed • PMOS transistors identified by a small circle around the poly-diffusion intersection

45. VDD S G B MP D Vin Vout D G B MN S GND Stick Diagram Notation VDD Vout Vin GND

46. Mixed Notation C B A C

47. Standard Cells • Modularized approach for layout • Follows certain guidelines in designing these modules • Each module represents a basic combinational or sequential logic function. • Each module has a standard height and variable width referred to as Standard Cell • A collection of these cells referred to as a Standard Cell Library • ASIC Designers deal with abstracted representation of these cells to construct a complete design • The abstracted representation is referred to as the Foot Print • Each abstracted representation consists of input and output terminals referred to as I/O Ports Foot Print Cell Name I/O ports

48. Standard Cells Output port Input port

49. VDD INV OUTPUT INPUT VSS Standard Cells Output Port Input Port

50. Standard Cells For DLM process, vertical routes use metal II. Horizontal routes use Metal I Notice the connections between Metal I and Metal II For Multi-level metal processes cell rows are flipped and butted. Routing can be made on top of the cell rows Routing Channel (More to come in section 5)