GRAND Status – Nijmegen Front-end, board design and firmware

1. GRAND Status – Nijmegen Front-end, board design and firmware

3. GP300 Nijmegen board design – short overview • ZYNC ZU7EG SOC-FPGA • Application processor: • - Dual core Cortex A53, 1.5Ghz • Real-Time processor: • - Dual core Cortex R5, 600MHz • ADC • - AD9694 16 bit, 500MSPS • Low jitter clk • - Si5340, 90 fs rms jitter • 20+ supplies • Highly configurable, on-line readout, low noise (for ADC and clock chip) • 2 DDR4 interfaces • 1 GB, 32b interface connected to PS • 512 MB 16b interface connected to PL • 10, 100 or 1000 Mb/s ethernet interface

4. GP300 Nijmegen board design - setbacks Setbacks: • Factoryproducedthe board withpreliminary files. (green PCB) • Three suplliesshoweddestructiveoscilationafterenabling output. • Selected FPGA (XCZU5) was notavailable. An upgrade, the XCZU7, is used in stead. • 200+ componentswerenotplacedduringproduction. • Short between a ground via and a 1V8 power line in aninternallayer of the board.

5. GP300 Nijmegen board design – current status • Allsupllies are workingandcanbeconfiguredby software. • Board is producedbased on correct files anddeliveredto Nijmegen (blue PCB). • Coming weeks: • Configureand test theclocks, JTAG, I2C and SPI. • Program the FPGA andbring up the processor system

6. Status filter design • - Filter design is finished • Fine-tuning done with real components Next step: • Create test board and measure filter performance

7. Status firmware and software Firmware Until the prototype is operational all firmware is developed for the reference board bought from Xilinx. - High speed ADC readout (JESD204B interface) is designed but needs debugging. - Firmware for DDR4 memory test is build. Will be tested coming weeks. - Firmware for triggering and data packaging is available but must be copied and modified from the previous Auger digitizer. Needs to be started. Processor system / Software Basic Linux kernel can be build and loaded in Xilinx ref board. To do: - include ADC readout in kernel - interface to memories - migration software Auger digitizer - readout sensors (pressure, humidity and temperature)

8. Firmware setup Processor System (PS) Clocks FPGA – Programmable logic (PL) GTH TCVR TX/RX ADC readout Ring buffer A ADC PL – PS interface Ring buffer B Data packaging Trigger logic GPS Slow control – Power – Sensor DDR interface Config: JTAG, SPI, I2C Housekeeping DMA PL – DDR4 PS – DDR4

9. Thank you for your attention

10. Backup slides

11. Chances for other contributors TO DO GP300 • Task list and needs: • Infrastructure • Mechanics 300 stations • Design / build 600 LNA's for 200 stations • Test setup • Transport andinstall TO DO GP300+ • Task list and needs: • Design low power LNA's • New communication to DAQ, alternative for the ubiquiti bullet – rocket solution (less power and cheaper). • New T2 coincidence trigger. p.e. sub group of 4-6 stations create 1 T2 trigger. This would require a new communication setup between antennas. (spec: 1km range, minimal 4kB/s BW) • ASIC integration ???

12. Status filter design 12 Apr 2019