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Digital Fields Board

Digital Fields Board. Wesley D. Cole (Hardware Design Engineer) Laboratory for Atmospheric and Space Physics University of Colorado at Boulder. EFW-DFB Organization. EFW – DFB Scientist Bob Ergun. Program Management Mary Bolton. Systems Engineering Susan Batiste. DFB – EE Wes Cole.

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Digital Fields Board

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  1. Digital Fields Board Wesley D. Cole (Hardware Design Engineer) Laboratory for Atmospheric and Space Physics University of Colorado at Boulder

  2. EFW-DFB Organization EFW – DFB Scientist Bob Ergun Program Management Mary Bolton Systems Engineering Susan Batiste DFB – EE Wes Cole FPGA – EE Ken Stevens Parts Engineer Cat Brant QA Trent Taylor System Validation David Malaspina FPGA – EE David Summers FPGA – Verification Magnus Karlsson

  3. EFW Block Diagram You Are Here

  4. EFW-DFB Functions Anti-alias filtering Analog signal buffering and attenuation 24 analog signals are routed to two ADCs by the multiplexer Digitization of analog signals DSP functions provided by FPGA (Ken Stevens) Interface to DCB

  5. Electric Fields Requirements

  6. EMFISIS SCM and MAG Requirements

  7. General Instrument Requirements

  8. EFW-DFB Performance Specifications

  9. EFW-DFB Performance Specifications

  10. EFW-DFB Interface Documentation DFB-IDPU Mechanical ICD (RBSP-IDP-MEC-200 DFB ICD Rev K) DFB Specification (RBSP_EFW_DFB_001D_SPEC Rev D) AXB and SPB signals (Interface with BEB) Interface with DCB Interface with LVPS Interface through backplane DFB FPGA Specification EFW to EMFISIS Electrical Interface Control Document (RBSP_EFW_to_EMFISIS_ICD_revA.doc) SCM and MAG signals from EMFISIS

  11. EFW-DFBResources Mass and Power Requirements Mass CBE based on measured mass of EM board Power CBE based on measurements and analysis of current design Housekeeping Telemetry Requirements DFB produces no analog housekeeping FPGA diagnostic housekeeping sent to ground on request Commanded through DCB

  12. Changes Since PDR Board Changes Added second SRAM for 1PPS buffering Removed ADC power switching Modified analog buffer circuits for better crosstalk performance Increased value of DC blocking capacitor for AC channels to increase bandwidth KA98 backplane connector Specification Changes V#AC (Burst 2) measurement range expanded from ±10 V to ±12.5 V E##AC (Burst 2) measurement range corrected to ±400 mV/m FPGA Changes Reworked packets to add EMFISIS Magnetometer back-up capability Solitary Wave Counter defined Added (V1DC + V2DC + V3DC + V4DC) / 4 data product to FFT (SPEC) and Filter Bank Changed number of frequency bands in FFT (SPEC and XSPEC)

  13. EFW-DFB Block Diagram

  14. EFW-DFB Component Derating * These capacitors have been procured to S-311-P-829 with Group B testing.

  15. EFW-DFB Component Derating

  16. EFW-DFB Thermal Requirements APL provides thermal control of IDPU EFW-DFB operational test limits (+55°C to -25°C) Component power dissipation FPGA: 394 mW LTC1604: 167 mW, Duty Cycle: 0.75 (Active / Nap Mode)

  17. EFW-DFB Testing Frequency response of analog filters Amplifier gain and offset Common-mode rejection Adjacent channel crosstalk Noise floor Square wave response Clamping diode response ADC accuracy Power consumption Verify commanding functionality Test of each flight configuration FPGA DSP testing (spectra, cross-spectra, solitary wave, field rotation) Backplane interface test Over-clocking End-to-end test Temperature testing EMI testing Pre-delivery testing

  18. EFW-DFB GSE Block Diagram

  19. EFW-DFB GSE

  20. EFW-DFB Test Results

  21. Active Filter Sallen-Key, 5-Pole, Low-Pass, Bessel, fc = 6.5 kHz Passband gain = 1, Linear phase and constant group delay (to preserve waveform shape in passband) Used 24 times in design

  22. Frequency Response (Gain and Phase)

  23. Square Wave Test Results Input: 1 kHz 1 V square wave 1% overshoot

  24. Sine Wave Test

  25. Sine Wave Spectrum

  26. Diode Clamping Test

  27. Diode Clamping Spectrum

  28. EFW-DFB Noise Test

  29. Crosstalk Test Results Input: 1 kHz, 4.9 VPP or 9.5 VPP sine wave on input channel, all others terminated by 50 Ω resistor.

  30. Materials & EEE Parts Status Materials Identification List Up-to-date Regular meetings with MPCB Need to add PWB data when ordered (will be per required IPC specs) Fasteners need to be approved EEE Parts List Up-to-date Regular meetings with PCB No issues Ordering status 42 received 8 on-order (due 11/10/09 at latest) 2 to be ordered (SRAM and bidirectional transceiver, due mid-December) 4 to be supplied by UCB (backplane connector, voltage regulators, EMFISIS connector) 1 to be supplied by APL (FPGA) 352

  31. Current Status DFB Flight schematics and layout complete DFB Flight printed circuit boards being fabricated DFB ETU #3 will be assembled in October with mostly Flight parts - testing will start in late-October First DFB Flight board will be assembled in December although work may start sooner

  32. EFW-DFB Backup Slides

  33. Radial and Axial Boom Signals Input signal range: ± 225 V Accuracy: 0.3 mV/m (for 100 m booms => 80 dB CMRR) Vishay 100-267T decade divider (1/100), Ratio tolerance: 0.01%, Input impedance: 1 MW, 300 V, 100 mW/resistor Same part used by THEMIS

  34. EMFISIS Signals and Differential Amp Gain accuracy: 80 dB, Resistor tolerance: 0.01% Vishay PHR foil resistors

  35. Multiplexer Signal Lists Channel 1 SignalsChannel 2 Signals V1DC V1AC V2DC V2AC V3DC V3AC V4DC V4AC V5DC V5AC V6DC V6AC E12DC FM1 E34DC FM2 E56DC FM3 E12AC SC1 E34AC SC2 E56AC SC3 Channel 1 signals meet the minimum science requirements

  36. Analog to Digital Converter Linear Technology LTC1604AIG 16-bit parallel output, Sample rate: 333 ksps (256 ksps required) Successive approximation register with internal sample and hold Internal clock Internal reference (15 ppm/degree C) S/N ratio: 87 dB minimum, THD: -100 dB typical Integral linearity error: ± 2 LSB maximum Operating temperature range: - 40 degrees C to + 85 degrees C Manufactured on Mil-Spec line to Class S plastic specification Radiation tested, no latchup protection required Redundant cross-strapped design, either ADC can measure any signal Flown on THEMIS

  37. Low Dropout Voltage Regulators MS Kennedy MSK 5922 K RH (1.5 V and 3.3 V) Total ionizing dose: 300 krad Backplane supply voltages: 1.8 V and 3.6 V Dropout voltage (from datasheet): 0.40 V max @ IOUT = 2.5 A Current manufacturer testing indicates a dropout voltage of only 0.15 V @ IOUT = 0.5 A MS Kennedy added specification: 0.3 V max @ IOUT = 0.5 A

  38. FPGA and SRAM Actel RTAX2000SL Used for DSP functions, ADC and Mux control, SRAM interface and backplane interface 2,000,000 equivalent system gates Total ionizing dose: 300 krad 1.5 V core voltage, 3.3 V I/O voltage Honeywell HLX6228 Used for DSP scratchpad Organized as 128K word x 8-bit Static RAM 32 ns read/write cycle times Typical operating power: < 9 mW/MHz Total ionizing dose: 1,000 krad No latchup

  39. EFW-DFB Signal Range

  40. EFW-DFB Signal Gains

  41. EFW-DFB Power Consumption

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