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Development of Readout ASIC for Pair-monitor with SOI

Development of Readout ASIC for Pair-monitor with SOI. Yutaro Sato Tohoku Univ. 21 Oct. 2009. Pair-monitor. Pair-monitor is a silicon pixel detector to measure the beam profile at IP. The distribution of the pair B.G. is used. The same charges with respect to the

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Development of Readout ASIC for Pair-monitor with SOI

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  1. Development of Readout ASICfor Pair-monitor with SOI Yutaro Sato Tohoku Univ. 21 Oct. 2009

  2. Pair-monitor Pair-monitor is a silicon pixel detector to measure the beam profile at IP. • The distribution of the pair B.G. is used. • The same charges with respect to the oncoming beam are scattered with large angle. • The scattered particles have information on beam shape. • The location will be in front of the BeamCal. e+ Distribution of pair B.G. BeamCal e+ beam IP 1σx (nominal) LumiCal 2 σx e- beam e- Y [cm] Y [cm] IP BeamCal Pair-monitor X [cm] X [cm]

  3. Development of Pair-monitor with SOI technology SOI (Silicon On Insulator) pixel detector • The sensor and electronics are integrated in the SOI substrate. • Monolithic device, high speed, low power, thin device, low material → Monolithic device allows the elimination of bump-bonding process. electronics SiO2 sensor • Pair-monitor • Pixel size : 400 x 400 μm2 • Radius : 10 cm • Total number of pixel : ~200,000 We started to develop the pair-monitor with SOI technology. As the first step, only the readout electronics was produced.

  4. Development of the readout ASIC Design concept of readout ASIC • Pair-monitor measures the hit distribution of the pair B.G.. • Measurement is done for 16 parts in one train for the time-dependent measurement. • 16 hit counts are stored at each part. • Count rate : < 2.5 MHz / (400μm x 400μm) • Information of the energy deposit is not necessary. • Data is read out during inter-train gaps. ( ~ 200 msec ) Beam structure 1 train = 2625 bunches ………………… …… [ [ [ 1 2 16 ~ ~ 1 msec 200 msec The prototype readout ASIC was designed to satisfy these concepts.

  5. Design of readout ASIC Layout of prototype ASIC Design of readout ASIC • 9 (3x3) readout pixels • Amplifier • comparator • 8-bitcounter • to count the number of hits • 16 count-registers • to store hit counts • Shift-register • to select a pixel from 9 pixels Readout pixel Output Input Amplifier comparator 8-bit counter Count-register 1 Count-register 2 … Count-register 16

  6. Prototype of SOI chip The prototype of the SOI chip was developed. Prototype chip • FD-SOI CMOS 0.2 μmprocess • Chip size : 2.5 x 2.5mm2 • # of pixel: 9 ( = 3x3 ) • Only the readout ASIC was fabricated. • Package : QFP80 Packaged ASIC The production of the readout ASIC was done in Aug. 2009.

  7. Test system The operation test was performed. Test system • GNV-250 module was used for the operation and readout . • KEK-VME 6U module • The test-sequence by GPIO is controlled by a PC. GPIO Test-board Operation Signals Readout ASIC Operation signals PC FPGA FIFO Hit count Hit count

  8. Response of shift-register The response of the shift-register was checked. • The select signal rose at the third clock signal. XCK SELECT YCK Gate Sig. Clock Sig. Selected Cell SELECT Select Sig. The shift-register works correctly.

  9. Response of pre-amplifier The output of the pre-amplifier was checked. Readout pixel Shaping -amp. 8-bit Counter Conunt- register x16 Pre-amp. Comparator Feedback capacitance : 0.1 [pF] Feedback capacitance: 0.05 [pF] TP timing TP timing Output from pre-amp. Output from pre-amp. The output from pre-amplifier was observed. As expected, the gain was larger for smaller feedback capacitance.

  10. Response of shaping-amplifier The output of the shaping-amplifier was checked. Readout pixel Shaping -amp. 8-bit Counter Conunt- register x16 Pre-amp. Comparator Pole-zero cancellation ON Pole-zero cancellation OFF TP timing TP timing Output from shaping-amp. Output from shaping-amp. The pole-zero cancellation works correctly.

  11. Response of counter block The response of the 8-bit counter was checked. • Gray code is used. • two successive values differ in only one bit. Readout pixel Shaping -amp. 8-bit Counter Conunt- register x16 Pre-amp. Comparator TP timing Q1 Binary-code Gray-code Q2 000 001 010 011 100 000 001 011 010 110 Q3 The counter block works correctly.

  12. Readout of hit counts Readout of hit counts was checked. • The hit count was stored at 4 MHz hit rate/ (400μm x 400μm) and read out from the countregisters. Readout pixel No bit-lost! Input Amplifier # of readout hit counts Counter Count-register1 Count-register2 @4MHz … Count-register16 The correct hit counts were read out from count-register. # of input TP

  13. Noise characteristic (1) Threshold scan was performed. • Fit to error function (S-curve) • Threshold : 6.886 ± 0.009 [mV] • Noise : 0.7152 ± 0.0128 [mV] • The gain was estimated to convert the noise into equivalent noise electrons. • Gain : 16.94 [mV/fC] (Injected charge 5.88 [fC]) Error function Threshold[mV] Count efficiency Noise Slope → gain Threshold Injected charge [fC] Threshold voltage[mV] Noise : ~260 electrons

  14. Noise characteristic (2) The noise level was checked as a function of the detector capacitance. • Each cell have different detector capacitance. →The noise level is 250 ~ 700 electrons. Noise [e] Exp. TSpice Sim. Noise is much smaller than typical signal level (~20,000 [e]) Detector capacitance [pF]

  15. Stability of noise The stability of the noise was checked. • The noise was evaluated in adjusting the time constant of amplifier circuits. Time constant of pre-amp. (VGGP) Time constant of shaping-amp. (VGGS) ( VGGP = -200[mV] ) ( VGGS = 80[mV] ) Noise [e] Noise [e] Design value Design value VGGS [mV] VGGP [mV] The noise level is stable (does not changed greatly).

  16. Pair-monitor for Belle II ? The availability of the pair-monitor for B-physics experiment @KEK (Belle II) was studied. Simulation Setup • Tools • CAIN (Pair-background generator) • Jupiter (Tracking emulator) • Virtual detector 1.1 m away from IP. IP Virtual detector Pair-monitor and BeamCal

  17. Hit distribution of pair background The hit distribution of the pair-background was checked (@200bunches). → The total number of hits (Nall) has information of σy. Hit distribution 1/Nall v.s. σy e+ e- Beam pipe Principle demonstration of the pair-monitor seems to be possible. To be more precisely studied.

  18. Summary • Pair-monitor is a silicon pixel detector to measure the beam profile at IP. • The development of the pair-monitor with SOI technology was started. • The first prototype which is only readout ASIC was produce. • The operation test was performed. • All the ASIC components work correctly. • The noise level is much smaller than typical signal level. • The availability of the pair-monitor for Belle II was checked. • Principle demonstration of the pair-monitor seems to be possible. • To be more precisely studied. • The irradiation test will be performed next month. Plan

  19. Thank you for listening!

  20. Backup

  21. Crossing angle • Large crossing angle leads to high momentum (px). Small crossing angle Large crossing angle e- beam e+ beam

  22. Nominal e+e- hit Crossing angle 14[mrad] 30[mrad] 50[mrad] 80[mrad]

  23. Total number of hits 1/Nall v.s. σy 1/Nall v.s. σx

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