Performed by: Tomer Michaeli 052792769 Liav Cohen 301242509

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות characterization of synchronizers and metastability Performed by: Tomer Michaeli 052792769 Liav Cohen 301242509 Instructor: Shlomo Beer Gingold Cooperated with: Winter 2010 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract • Recent meta-stability measurements down to 65nm technologies indicated increase of MTBF (Mean Time Between Failures) with technology scaling. • As opposed to those conclusions, later on-chip measurements on up to 65nm technologies showed degradation of MTBF with technology scaling [2]. • This project deals with off-chip measurements of Flip Flops (FF’s) parameters [1] and comparison to the on-chip measurements (in 65nm technology) [5]. • The FFs are included in the synchronizer circuits (synchronizers), hence the parameters have high importance in system reliability. • The two main parameters that are calculated: Tw , (resolution time constant). • Notice that is predominant since its effect on MTBF is exponential. 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram and Description Fd [Hz] Choosing one of the synchronization circuits :-regular FF -synchronizer 1 -synchronizer 2 Fc [Hz] Calculating the delay between clock rising to data rising by the scope F_data=(Fc-Fd)[Hz] Data (TRIGGER) PC TRIGGER 3.125MHz \ 6.245MHz DSO80204B Scope synchronizer clock (Input) Input 6.25MHz Getting the measurements values from scope to PC by VEE program 5

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Measurements • Measurements were performed at Vdd=1.1V and room temperature. • 2 DATA frequencies 3.125 [MHz] and 6.245 [MHz] were measured and clock frequency 6.25 [MHz] • Measurement period time: T=200 [sec] for each delay value. • Measurements were executed on 3 different chips • Calculating ,by the scope , the delay between the DATA signal • (synchronizer output) and the clock signal (Ch1-Ch2), which mean the delay between clock rising to the data stabilizing. • Getting the measurements values from the scope to PC by VEE program (with GPIB connection). 3

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specification • Hardware • An oscilloscope that can create histograms • FPGA board • DLP daughter board. • Signal generator • Voltage regulator • Test chip board • PC, including Xillinx ISE, Visual Studio. • Software • MATLAB 4

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות References Yaron Semiat and Ran Ginosar, ‘Timing Measurements of Synchronization Circuits’ , Technion, Haifa, 2003. Shlomo Beer Gingold, ‘Test Chip (Sinc_test_chip)’, Technion, Haifa. Salomon beer ,Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin and Avinoam Kolodny, 'The Devolution of synchronizers', Technion, Haifa, 2010. Lindsay Kleeman & Antonio Cantoni, 'Metastable Behavior in Digital Systems' , University of Newcastle, New South Wales, 1987. Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin and Avinoam Kolodny, 'An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm' , Technion, Haifa. DLP Design, 'DLP-USB245M-G USB to FIFO Parallel Inetrface Module', 1605 Roma Lane, Allen TX 75013. 'Xilinx University Program Virtex-ll Pro Development System', UG069 , March 8,2005 6