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Synch vs. Asynch set & reset

library ieee; use ieee.std_logic_1164.all; entity ffctrl is port ( -- System Clocks and reset arst_n : in std_logic; -- Main clock reset mclk : in std_logic; -- Reference clock -- Input signals set_in : in std_logic;

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Synch vs. Asynch set & reset

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  1. library ieee; use ieee.std_logic_1164.all; entity ffctrl is port ( -- System Clocks and reset arst_n : in std_logic; -- Main clock reset mclk : in std_logic; -- Reference clock -- Input signals set_in : in std_logic; enable_in : in std_logic; data_in : in std_logic_vector(7 downto 0); -- Output signals reg_data_arst : out std_logic_vector(7 downto 0); reg_data_srst : out std_logic_vector(7 downto 0) ); end ffctrl; Synch vs. Asynch set & reset INF3430 H13

  2. Synch vs. Asynch set & reset P_RST_SYNCH : process(arst_n, mclk) begin if arst_n='0' then rst_s1_n <= '0'; rst_n <= '0'; elsif rising_edge(mclk) then --sync deactive rst_s1_n <= '1'; rst_n <= rst_s1_n; end if; end process P_RST_SYNCH; INF3430 H13

  3. P_REG_ARST: process(rst_n, mclk) begin if rst_n='0' then reg_data_arst <= (others => '0'); elsif rising_edge(mclk) then if set_in='1' then reg_data_arst <= (others ’1’); elsif enable_in='1' then reg_data_arst <= data_in; end if; end if; end process P_REG_ARST; P_REG_SRST: process(rst_n, mclk) begin if rising_edge(mclk) then if rst_n='0' then reg_data_srst <= (others => '0'); elsif set_in='1' then reg_data_srst <= (others => '1'); elsif enable_in='1' then reg_data_srst <= data_in; end if; end if; end process P_REG_SRST; Synch vs. Asynch set & reset INF3430 H13

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  5. Synch vs. Asynch set & resetActel techn. 1 INF3430 H13

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