Logic Simulator for Hierarchical Bench

1. Logic Simulator for Hierarchical Bench Hillary Grimes III – Term Project ELEC 7250 – Spring 2006 ELEC7250 Project: Grimes

2. Problem Statement • Develop a Logic Simulator for Zero-Delay Boolean gates to perform circuit verification. • Inputs: --Hierarchical Bench Circuit Description --Input Vectors and Expected Outputs • Outputs when Simulation Fails: --Inputs and Outputs with failed responses --Diagnosis Information ELEC7250 Project: Grimes

3. Signals Contain: --signal name --level --value Gates Contain: --gate name --gate type --level --input signal list --output signal list --fan in array Circuit Representation in C • Each hierarchical block is stored as an element in a block array containing:--block name --input signal list --array of gates --output signal list ELEC7250 Project: Grimes

4. Building the Block Array • Each block is flattened as it is read in • After POs and PIs are assigned, the gate array is built. Each line from the netlist is either a boolean gate, or a previously defined block. -If boolean gate – add to gate array --gate name: “g0, g1, g2, etc” --assign input and output signals -If not boolean – insert block from previous elements in block array ELEC7250 Project: Grimes

5. Insert Gates for an XOR Block XOR Description: Inputs: A, B Output: Y X1=NAND(A,B) X2=NAND(X1,A) X3=NAND(X1,B) Y=NAND(X2,X3) XOR Block’s gate array contains: g0: NAND g1: NAND Inputs: A, B Inputs: X1, A Output: X1 Output: X2 g2: NAND g3: NAND Inputs: X1, B Inputs: X2, X3 Output: X3 Output: Y OUT = XOR ( IN_1, IN_2) Inserts Gates: XOR0.g0: NAND XOR0.g1: NAND Inputs: IN_1, IN_2 Inputs: XOR0.X1, IN_1 Output: XOR0.X1 Output: XOR0.X2 XOR0.g2: NAND XOR0.g3: NAND Inputs: XOR0.X1, IN_2 Inputs: XOR0.X2, XOR0.X3 Output: XOR0.X3 Output: OUT ELEC7250 Project: Grimes

6. Level Block • Gates are inserted into gate array such that each gate’s inputs are either PIs, or an output of a previous gate. • To levelize a block, we visit each gate in increasing order: --level of gate = max level of input signals --level of gate’s output = 1+gate level --increasing order ensures that each input has an assigned level ELEC7250 Project: Grimes

7. Simulation • To simulate a block given an input vector: --assign signal values to primary inputs --visit each gate in gate array (increasing order): -evaluate and assign gate’s output signal • Diagnose if output differs from the expected response --diagnoses starts at each failing PO and back tracks through the circuit --information (including signal values) for each gate along a path to the failing PO is printed ELEC7250 Project: Grimes

8. Results ELEC7250 Project: Grimes

9. Results ELEC7250 Project: Grimes

10. Conclusion • Execution times seem to grow with both the number of gates, and the number of inputs/outputs • Diagnosis still needs work --if multiple paths to the failing PO include the same gate, that gate’s information is printed multiple times. --diagnostic resolution could be much better with a better algorithm ELEC7250 Project: Grimes