A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets

1. A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets A. V. S. S. Prasad Agere Systems, Bangalore 560066, India avssp@agere.com Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 07974, USA va@agere.com Madhusudan V. Atre Agere Systems, Bangalore 560066, India mvatre@agere.com Prasad et al., ITC'02

2. Talk Outline • Introduction • Background • Problem statement • A new graph model • Dominance graph • Transitive closure • Extraction of equivalence and dominance sets • Functional equivalence • Hierarchical fault collapsing • Benchmark results • Conclusion Prasad et al., ITC'02

3. Test Vector Generation Flow DUT Generate fault list Collapse fault list Generate test vectors Fault Model Required fault coverage Prasad et al., ITC'02

4. a0 = b0 = c0 : Equivalence a1 c1 : Dominance b1 c1 : Dominance Background • Single stuck-at fault model is the most popularly used model. • Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2 (f1=f2) • If all tests of fault f1 also detect fault f2, then f2 is said to dominate f1 (f1f2). a0 a1 c0 c1 b0 b1 Prasad et al., ITC'02

5. Background • Both equivalence and dominance relations are transitive in nature. [ (f1  f2) and (f2  f3) => (f1  f3) ] • If f1 dominates f2 and f2 dominates f1 then f1 and f2 are equivalent. [ (f1  f2) and (f2  f1) => (f1 = f2) ] • Number of faults in a 2-input AND gate reduces from 6 to 4 (by equivalence) and to 3 (by dominance) collapsing. Example: ISCAS’85 Circuit - C6288, #faults = 10630, #faults (dominance collapsed) = 5824 Prasad et al., ITC'02

6. Problem Statement • To devise a new method for fault collapsing with following attributes: • A single procedure for equivalence and dominance • Global analysis (independence from direction, and other choices, in collapsing) • Functional equivalence • Hierarchical fault collapsing (collapsing in large circuits using pre-collapsed sub networks) Prasad et al., ITC'02

7. A New Dominance Graph Model • A fault in the circuit is represented by a node in the graph. • A directed edge from f2 to f1 indicates that f1 dominates f2 (f2 f1). • Edges can represent either structural or functional relations. Prasad et al., ITC'02

8. Computational Model • Graph is represented as a connectivity matrix • Each fault is assumed to be equivalent to itself • Treats functional and structural relations identically • (f1  f2) and (f2 f1) => f2 = f1. Appear as symmetrical components in the matrix (e.g., a0,b0,c0) • #faults = 6 (dimension of dominance matrix) 2-input AND gate Prasad et al., ITC'02

9. Transitive Closure • Transitive closure (TC) of the dominance matrix gives all dominance relations between faults. • TC is computed by the O(n3) Floyd-Warshall algorithm, where n is the dimension of the dominance matrix. Prasad et al., ITC'02

10. F1 F1 F2 F2 F3 F3 F1 F1 1 1 1 1 1 F2 F2 1 1 1 1 F3 F3 1 1 F1 F2 F3 F1 F2 F3 Graph Transitive Closure Transitive Closure • (F1  F2) and (F2  F3) => (F1  F3) Prasad et al., ITC'02

11. Transitive closure edges C1 E1 D1 B1 C0 E0 B0 D0 Example A D E B C Dominance Graph A0 A1 Prasad et al., ITC'02

12. XOR Circuit c1 h1 g1 m0 g0 i1 f1 Functional Equivalences : (c1,f1), (g1,h1,i1), (g0,m0) Prasad et al., ITC'02

13. Dominance matrix (XOR) (24x24) Functional equivalences shown as boxed entries Prasad et al., ITC'02

14. Transitive Closure (XOR) j0 k0 m1 f1 f0…c1 a0 Prasad et al., ITC'02

15. With functional equivalence #faults #Eq. Faults #Dom. faults 24 12 10 Results for XOR Circuit Prasad et al., ITC'02

16. Summary of Approach • Identify all the primary relations (structural and functional) • Construct the dominance graph and represent the same using connectivity matrix • Compute Transitive Closure (TC) • Extract equivalence and dominance sets from TC Prasad et al., ITC'02

17. Features • Global in nature (single procedure to treat equivalence and dominance collapsing) • Functional relations can easily be incorporated • Independent of the order of selecting the faults Prasad et al., ITC'02

18. Design Hierarchy • Large designs are modular and hierarchical. • Advantageous to store the fault information of repeated blocks in a library. • When configured as a library cell the fault list includes cell PI & PO faults for transitivity. Top module B1 B1 B0 C0 C0 C0 C0 C1 C1 Prasad et al., ITC'02

19. XOR Library Cell • Useful for hierarchical fault collapsing • Dimension of the matrix = 14 Prasad et al., ITC'02

20. 8-bit Ripple Carry Adder (RCA) Prasad et al., ITC'02

21. Faults in 8-bit RCA Circuit name All faults Prasad et al., ITC'02

22. ISCAS’85 Circuits * Fastest, Gentest, Hitec, TetraMax Prasad et al., ITC'02

23. Conclusion • A new algorithm for global fault collapsing • With functional equivalence number of faults for ATPG reduces considerably • Library based hierarchical fault collapsing is a new concept • Further studies are being carried out on: • Functional dominance • Independent fault sets Prasad et al., ITC'02