Physical Design of FabScalar Generated Cores

1. Physical Design of FabScalar Generated Cores EE6052 Class Project Wei Zhang

2. Outline • FabScalar Toolset • Synthesis • Physical design using IC Compiler – Problems and solutions • Things to do next Wei

3. FabScalar Toolset • FabGen: This tool generates synthesizable RTL of a superscalar core based on user-specified parameters:* Frontend superscalar width* Backend superscalar width* Pipeline depths of canonical pipeline stages* Issue queue size. • FabMem: This tool estimates read/write delays, read/write energies, and area of user-specified multi-ported RAMs/CAMs. It can also generate layouts of desired RAMs/CAMs. Wei

4. Synthesis • FebGen-generated RTL is synthesizable. • Before starting synthesis • Comment-out the verification components to remove unsynthesizableverilog needed for simulation only: VPIs (the verilog/C++ co-simulation environment) and performance counters. • Memory handling • Use FabMem to generate custom designs of these critical memory structures, including full layouts, SPICE netlists, and LEFs. • During synthesis, remove the behavioral modules of the memory structures and constrain their input-port and output-port timing paths based on timing numbers from SPICE simulation. • For place-and-route, use the LEFs to represent the memory structures. Wei

5. Physical Design – Problems Encountered • ICC reports errors when importing netlist generated from synthesis. • Error message examples from ICC • Error: Can not create instance master 'SRAM_4R8W' in FRAM view. (MWDC-001) • Error: Can not create instance master 'CAM_4R4W' in FRAM view. (MWDC-001) • Warning message examples from synthesis • Warning: Unable to resolve reference 'SRAM_4R8W' in 'InstructionBuffer'. (LINK-5) • Warning: Unable to resolve reference 'CAM_4R4W' in 'IssueQueue'. (LINK-5) • Cause of the errors • No corresponding memory cells in the Milkyway library. Wei

6. Physical Design – Problem Solutions • Solution 1 – Find memory instances from existing designs – OpenSPARC, ChipTop, Leon, and memories from SAED_EDK90nm. • The memory instances from these existing designs do not match the memories used in FabScalar cores, which are mostly multi-ported memories. • Solution 2 – Use memory blocks generated from the FabMem tool. • The FabMem tool uses the FreePDK 45nm library which does not match the 90nm technology library used in ICC. • It is very difficult to change the FreePDK 45nm library to 90nm technology library in FabMem. • Solution 3 – Change to the FreePDK 45nm library for the physical design. • Synthesis could be done using FreePDK. But the FreePDK 45nm library could not be utilized in ICC. Wei

7. Physical Design – Problem Solutions • Solution 4 – Adapt the memory blocks generated from the FabMem tool to the 90nm technology. • The FabMem tool could generate layouts of memories, from which we can get the GDSII files. • To adapt these layouts to the 90nm technology, we need to modify the GDSII files to • Double the size of each physical component in the layout. • Map each layer in the FreePDK library to these layers in the 90nm technology library. • Import these memory blocks to the Milkyway Library using the Milkyway Environment tool and the new GDSII memory files. Wei

8. Milkyway Environment • The Milkyway Environment is a standalone tool for preparing physical libraries from the layout data provided by an outside source. Wei

9. Library Preparation Flow in the Milkyway Environment Wei

10. Changing GDSII Layers Wei

11. Things To Do Next • Adapt memories to the 90nm technology and import them to the Milkyway library. • Proceed with the physical design. Wei