Solar Probe Plus FIELDS DCB FSW Preliminary Software Design

1. Solar Probe Plus FIELDSDCB FSW Preliminary Software Design Barbara Plante Peter Harvey University of California

2. Agenda • Preliminary Software Design • Flight Software Overview Hardware Context Detailed Design Functional description Structural decomposition Interface Design, Timing Commands and Telemetry Resource Margins • Data Structures, Timing, Logic

3. Overview Development Plan : SPF_SYS_008A Processor : 19 MHz ColdfireIP with 4 MB DRAM, 32 GB Flash Language: C & Assembly (Converted from RBSP, MAVEN) Deliveries: Boot (32K PROM), Operational (512K EEPROM) Requirements: 65 (Boot), 94 (Operational) Effort : ~8K-10K SLOC in 17 modules Major Functional Requirements: • Command Reception & Distribution • Engineering Housekeeping Telemetry • On-Board Limit Monitoring • Absolute & Relative Time Command Sequences • Real-Time Data Collection and Playback • Archive Data Collection and Playback • Data Compression • Controllers Electronics Circuits [LNPS1,AEB1,MAG1,RFS,DFB,TDS]

4. Hardware Context • FIELDS System Block Diagram • Two Sides • Each has Spacecraft I/F • Each has Magnetometer • Each has Antenna Elect. • Each has Power Supply • FIELDS1 also has • Radio FreqSpect. • Digital Fields Board • SCM Calib Control • Absolute Time Sequencer • TDS I/F • FIELDS2 also has • Time Domain Sampler • DCB I/F • SWEAP I/F

5. Hardware Context DCB Block Diagram

6. Design FSW Major Modules

7. Design FSW Major Modules

8. Boot/Initialization Hardware Reset • Power-On • WDRST -- Watchdog Reset (7-seconds) • SCRST – Spacecraft Reset (Commandable) Reset Sequence • FPGA Copies PROM into RAM • FSW Initializes All Variables and Begins at main() (EXEC module) • Issues Initialization Calls to Each Module • Starts in Safe Mode • Begins Engineering Telemetry (1-sec) • Checksums EEPROM programs • Selects first-program with Good Checksum • Waits Until 10 seconds elapsed time • Runs Selected Program • Reads Instrument Power Config., Sends Initial Sequence

9. Modes & Enables FSW Modes • Safe – Minimal Activities Allowed • Normal - FLASH Memory Allowed • Engineering – EEPROM Loading Allowed

10. Timing OLD SLIDE Interrupts • 256 Interrupts/ DCB Cycle (293 Hz) • Distributes CPU Time per Table • Basic ¼ second table repeats 4 times/DCB cycle • CMD gets 32 Hz • DFB gets 128 & 16 Hz, etc.

11. Data Collection OLD SLIDE Data Collection • DMA Channels are Assigned to Each Data Source • Based upon options, FSW determines data rate and length • FSW Writes Destination Addresses into Each DMA Controller • DMA Registers are Double-Buffered to Eliminate Gaps • DMA Buffers Automatically Swap at 1 DCB cycle (1 NY Second)

12. EEPROM

13. SRAM

14. S/C Interface • Command/Timing Information • Commands Use 115.2 KbaudAsync messaging • DMA channel input to 2 x 2048 byte buffers • S/C Inter-command gap of 10 msec • DMA Automatically switches buffers at 10 ms gap • FSW verifies FPGA transfer status (framing, parity, buffer overflow) • FSW verifies ITF format prior to decoding/using commands • FSW must initiate Safe Mode if [reference] • DCB FSW must tolerate time update gaps

15. S/C Interface • Telemetry Information • Telemetry Uses 345.6 KbaudAsync messaging • CCSDS packets (1 or more) packed into Instrument Transfer Frames (ITF) • Critical Housekeeping Messages at 1Hz in the first ITF of the second • Telemetry Must Complete with 10ms margin to next S/C 1PPS • Engineering Telemetry will use 2x8192 byte DMA buffers • Survey and Archive can be transferred directly from circular buffers • In Situ Data Compression of Selected APID’s in Survey and Archive buffers • Telemetry Rate Commandability to approximately 218 kbps • FSW will deliver Survey per Instrument configuration • Remaining Bandwidth Will be Used to Play Archive data

16. Telemetry Timing Playback Mode Enabled

17. Survey (Real-Time) Data RT Data Management

18. Archive Data Archive Data Recording FLASH Hardware 32 GB Capacity EDAC Enabled Write/Read DMA-Channel to/from SRAM Block Addressable 2^17 256KB Blocks Each Block has 4K extra bytes • EDAC • Bad-Block-Indicator • Erase Count Each 8 GB module Powered Separately FSW Functions Stores/Retrieves Archive Science Blocks (32 4K packets) Circular Memory with Separate Read & Write Ptrs Memory mapping at the Chip Level (256 elements = 256 chips) Playback Commanded by Block# and Length Both Read/Write Block pointers Telemetered at 1Hz (tbd) Ground S/W keeps MET-to-Block# relationship

19. Archive Data Archive Write/Read Buffer Management

20. Archive Data Archive Playback Selection

21. Archive Data Archive Virtual-to-Physical Mapping

22. FLASH Timing FLASH Timing

23. FLASH Logic Read/Write/Diag Decision State D0

24. FLASH Logic Read Logic States with Error Handling

25. FLASH Logic Write Logic State W1 with Error Handling

26. FLASH Logic Write Logic State W2 with Error Handling

27. Compression Compression Selected packet is compressed using 16-bit Delta-Modulator v2 Each waveform cut into 32-sample blocks Result is 1 raw 16-bit sample, 31 deltas The Width of the deltas is determined and the deltas are packed up Packet compression time shown below for varying widths Required : 12 kbps output Measured on RBSP: • [w=15]: 620 kbps • [w= 1] : 97 kbps

28. Compression In Situ Packet Compression (Survey and Archive)

29. Processor Utilization • Utilization • Measurements from MAVEN (in cycles) • Scaled to FIELDS rates and adjusted for CPU Frequency • FIELDS DCB runs at 19.2 MHz instead of 16 MHz • TDS &RFS processing only estimated using worst case MAVEN instrument processing (STATIC).

30. Issues Issues