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Shannon Tauro / Jerry Lebowitz

Introductory Computer Organization The Microarchitecture Level Tannenbaum 4.1.1, 4.1.2, 4.1.3. Shannon Tauro / Jerry Lebowitz. MicroArchitecture Level. MicroArchitecture Level Job is to implement the Instruction Set Architecture (ISA). Big Picture. Instruction Set Architecture (ISA).

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Shannon Tauro / Jerry Lebowitz

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  1. Introductory Computer OrganizationTheMicroarchitecture LevelTannenbaum 4.1.1, 4.1.2, 4.1.3 • Shannon Tauro/Jerry Lebowitz

  2. MicroArchitecture Level • MicroArchitecture Level • Job is to implement the Instruction Set Architecture (ISA)

  3. Big Picture

  4. Instruction Set Architecture (ISA) • Depends on ISA being implemented • Reduced Instruction Set Computing (RISC) • Complex Instruction Set Computing (CISC)

  5. Reduced Instruction Set Computing (RISC) • Strategy based on the insight that simplified (as opposed to complex) instructions can provide higher performance if this simplicity enables much faster execution of each instruction • Small, highly-optimized set of instructions • Used in SPARC, Power PC • ARM architecture processors in smart phone and tablets are based on RISC

  6. Complex Instruction Set Computing (CISC) • Where single instruction can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modes within single instructions • Used in Pentium, Core i7 processors

  7. Design of Microarchitecture • Want to: Explain general principles of micro-architecture design but THERE ARE NONE!! EACH IS UNIQUE

  8. Example MicroArchitecture • A subset Java Virtual Machine (JVM) for integer operations will be discussed • IJVM : Integer Java Virtual Machine • Our microarchitecture will contain a microprogram (in ROM) whose job is to: • Fetch • Decode • Execute IJVM instructions

  9. IJVM • Each instruction at the ISA level is a function that is called by a master program • Imagine the design of MicroArchitecture as the following code: • The microprogram has a set of variables • Values represent the STATE of the computer

  10. Example MicroArchitecture • IJVM Instructions: short; usually 1-2 fields • Every ISA instruction has an opcode • Many ISA instructions have operands • Model of Execution: fetch-decode-execute cycle Micro-instructions form the microprogram

  11. CPU CPU = Controller + Datapath • Datapath: contains • ALU • Registers • Inputs & outputs (not shown)

  12. Registers are only addressable at the microcode level IJVM Datapath MDR – memory data register MAR – memory address register MBR – memory buffer register – holds the instruction stream as it comes in from memory CPP – Constant pool pointer LV – Pointer to Local variables SP – Pointer to the top of the stack TOS – Contains the value of the memory location pointed to by SP OPC – Temporary register • Datapath: contains • 32-bit registers • Registers are accessible only by micro-program at the microArchitecture level • B-BUS: Contains the contents of registers • C-BUS: Contains the output of ALU • Can write to multiple registers at once

  13. Controlling Registers • Each of these registers are controlled by two signals • A solid arrow under a register indicates a control signal that writes (loads) the register from the C bus • An open arrow under a register indicates a control signal that enables the register’s output onto the B bus • To initiate a memory read or write, the appropriate memory register must be loaded, then a read or write signal issued to the memory

  14. IJVM Datapath • Datapath: contains an ALU: • Needs 2 inputs: A(left) register H (1 source) B(right) Bus B (9 sources)

  15. IJVM Arithmetic Logic Unit F0 and F1 used to determine the ALU operation ENA and ENB for individually enabling inputs INVA for inverting the left input INC forcing a carry into the low order bit (add 1 to the result) ALU Truth Table • ALU Operation: • To load H: • Choose an ALU function that • Passes the value at the B input through the ALU • Writes value back into H i.e. identity of B Sample inputs 6 ALU control lines

  16. IJVM Arithmetic Logic Unit • ALU Operation: • Read and write in same cycle • Can happen with magic and timing 1st half of cycle one reads register 2nd half one can write ALU Truth Table

  17. Memory Operations • Two ways to address memory • 32-bit word-addressable memory • Memory Address Register (MAR) • Memory Data Register (MDR) • The 8-bit byte-addressable port is controlled by the PC • Reads 1 byte into the low-order memory of the memory buffer register (MBR)- (read only port)

  18. Registers • MAR contains word addresses • 0,1,2,… refer to consecutive words • MAR/MDR: used to read/write ISA-level data words • PC contains byte addresses • 0,1,2,… refer to consecutive bytes • PC/MBR: used to read the executable ISA-level program (consists of a byte stream)

  19. MicroInstructions • ALU, registers, buses • All have control signals • IJVM data path • 29 signals are needed for one cycle of the data path • A cycle consists of gating values out of registers onto the B bus, propagating signals through the ALU and driving them on the C bus, and writing the results in the appropriate registers These signals together create the Binary Micro-Instruction

  20. Signals • Signals are divided up into 5 functional groups • 9 signals to control writing data from the C bus into registers • 9 signals to control enabling registers onto the B bus for ALU input • 8 signals to control the ALU and shifter functions • 2 signals (not shown) to indicate memory read/write via MAR/MDR • 1 signal (not shown) to indicate memory fetch via PC/MBR

  21. Memory Read Operation • 1st Bus Cycle: • Memory address is loaded into memory Address Register (MAR) • 2nd Bus Cycle: • Data is fetched from memory and stored in registers • 3rd Bus Cycle: • Data can now be used in an instruction • Note: • One can start another instruction during the 2nd bus cycle • One that does not need information from the previous read

  22. MicroInstruction Format • 36-signals correspond to one IJVM instruction

  23. MicroInstruction Format Groups Addr: Contains the address of a potential next microinstruction JAM: Determines how next microinstruction is selected

  24. MicroInstruction Format Groups • ALU: controls the ALU & shifter functions C: Selects which registers are written from the C Bus Mem: Memory Functions B: Selects the B bus source

  25. Finally…. • Here we are!!! Our Controller + Data path!!! 

  26. 4-16 Decoder • Decoder is a device which does the reverse operation of an encoder • Multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs • Converts the bits stored in the microinstruction – into the control signals that control the other parts of the CPU • 4 inputs -> 16 outputs

  27. Sequencer • Responsible for stepping through the sequence of operations necessary for execution of a single ISA instruction • Produces two kinds of information on each cycle • State of every control signal in the system • Address of the microinstruction that is to be executed next

  28. Control Store (ROM) • Can be implemented as a memory that holds the microprogram (memory cells) or logic gates

  29. Needs its own memory address register and memory data register (MPC) and MIR Doesn’t need read and write signals since it is continuously being read Control Store • Accessed through MBR and MDR • Holds microinstructions (not ISA instructions) • Properties: • 512 words • 1 word = 36-bit micro-instruction • Has it’s own address register: MicroProgram Counter (MPC) • Has it’s own data register: MicroInstruction Register (MIR)

  30. Important Difference…. • Main Memory: • Program Instructions; executed sequentially (except for branches) : • Incrementing the PC means execute the next instruction • Control Memory: • Each microinstruction explicitly specifies its successor • It is a Read Only Memory

  31. Micro Program Responsibilities • The microprogram needs to: • Drive the datapath • Determine which instruction to execute next

  32. Micro Program Responsibilities • To determine the next instruction… • Begins after MIR has been loaded and is stable • 1a) 8-bit next address field is copied to MPC • 1b) Inspect JAM field: • if 000  • do nothing, next instruction is initialized • if !(000) test JAMN & JAMZ • if (JAMN = 1 || JAMZ = 1) • 1-bit N and/or Z flip-flip is ORed • into high-order bit of MPC • MPC = (Value of Next Address) • or • (value of next address with high order bit OR-ed with 1) • Allows one to branch to another instruction

  33. Simulation… After MIR is stable Apply High Bit Result to MPC 1a 1b Test n & z

  34. An Example ISA - Stack Based Machine • Stack Based Machine: Operands are placed on a stack and the result is stored on the stack • SP: top of stack pointer • LV: pointer to local variables • The data structure between LV and SP is called a local variable frame

  35. Method Calls (Variables) Stored on a stack (b and c returns) LV LV LV LV a3 b3 b3 d3 a3 c3 a3 d6 a3 SP SP SP SP c2 a2 a2 a2 d5 b2 b2 a2 d2 a1 d1 a1 a1 a1 b1 c1 d4 b1 a b c d

  36. Method Calls (Operands) Stored on a stack • Want a1 = a2 + a3 • Push a2 and a3 on the stack • Pop a2 and a3, add them together and push the result on the stack • Pop the result and store it in a1 Note: Variables and operand can be intermixed on the stack

  37. IJVM Memory • Constant pool • Constants, strings, pointers to other area of memory (cannot be changed during execution) • Cannot be written to a IJVM program • Local variable frame • Used when methods are called (storing variable) • Operand stack • Part of the local variable frame • Method area • Where the program resides • Size • 4,294,967,296 bytes (4 GB)

  38. IJVM Instruction Set Each instruction consists of an opcode and sometimes and operand

  39. IJVM Instruction Examples • Push a word on a stack • LDC_W, ILOAD, BIPUSH • Pop off a stack • ISTORE, BOPUSH • Arithmetic • IADD, ISUB • Boolean • IAND, IOR • Branching • GOTO, IFEQ, IFLT, IF_ICMPEQ

  40. Compiling Java to IJVM corresponding corresponding Java Code IJVM assembly language Binary program

  41. Compiling Java to IJVM • First j and k are pushed onto the stack, added, and result is stored in i • Then i and the constant 3 are pushed on the stack and compared • If equal, branch to L1 where k is set to 0 • If not equal, the compare fails and the code following the IF_ICMPEQ is executed • When done, branch to L2

  42. Stack Progression k j j j+k 0 1 2 3 4 1 3 i i j j 5 6 7 8 9 j - 1 0 14 10 11 12 13 15

  43. Implementation needed • MicroArchitecture has been defined now we need to define an implementation

  44. An Example Implementation • Define a High-Level Micro Assembly Language (MAL) • Tailored to be consistent with the microArchitecture that was just defined • Simple assignment statements will be used to indicate operations • To copy something from SP to MDR • MDR = SP • To indicate the use of the ALU functions other than passing through the B bus • MDR = H + SP (add the contents of the H register to SP and writes the result into the MDR)

  45. High-level micro-Instructions

  46. Valid High-level Instructions • Need to define only valid operations • Valid sources are MDR, PC, MBR, MBRU (unsigned version of the MBR), SP, LV, CP, TOS, OPC • Act as sources to the ALU on the B bus • Valid destinations are MAR, MDR, PC, SP, LV, CPP, TOS, OPC, or H • Act as destinations for the ALU output on the C bus • The statement MDR = SP + MDR is illegal because the addition (other than increment or decrement) must involve the H register • The statement H = H - MDR is illegal because the only possible source of the subtrahend (the value being subtracted) is the H register

  47. High-level Instructions • There are only 112 valid microinstructions • Three columns • Symbolic label • Actual microcode • Comment • Note that consecutive microinstructions are not necessarily located in consecutive memory locations in the control store

  48. Valid Statements (1)

  49. Valid Statements (2)

  50. Valid Statements (3)

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