Latches and Flip-Flops

1. Latches and Flip-Flops Discussion D8.1 Section 13-9

2. Sequential Logic • Combinational Logic • Output depends only on current input • Sequential Logic • Output depends not only on current input but also on past input values • Need some type of memory to remember the past input values

3. Cross-coupled Inverters State 1 State 2

4. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 1 0 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

5. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 0 0 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

6. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 0 1 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

7. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 0 1 0 0 0 1 1 0 1 1 1 0 Set 0 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

8. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 1 1 0 0 0 1 1 0 1 1 1 0 Set 0 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

9. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 1 1 0 0 0 1 1 0 1 1 1 0 Set 0 0 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

10. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 1 1 0 0 0 1 1 0 1 1 1 0 Set 1 0 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

11. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 1 0 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 0 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

12. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 1 0 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

13. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 0 1 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 0 0 1 Store 1 0 Q0 !Q0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

14. ~S Q ~Q ~R ~S-~R Latch ~S ~R Q ~Q 1 0 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 Q0 !Q0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0 To close or lock with or as if with a latch, To catch or fasten

15. S CLK R S R CLK ~S ~R Q ~Q S-R Latch ~S Q ~Q ~R 0 0 1 1 1 Q0 ~Q0 Store 0 1 1 1 0 0 1 Reset 1 0 1 0 1 1 0 Set 1 1 1 0 0 1 1 Disallowed X X 0 1 1 Q0 ~Q0 Store

16. D S R CLK Q ~Q D CLK Q ~Q 0 0 1 Q0 ~Q0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 ~Q0 Store 0 1 0 1 1 1 1 0 X 0 Q0 ~Q0 D Latch S ~S Q CLK ~Q ~R R

17. D CLK Q ~Q 0 1 0 1 1 1 1 0 X 0 Q0 ~Q0 D Latch S ~S D Q CLK ~Q ~R R Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

18. ~S Q ~Q ~R Recall the ~S-~R Latch ~S ~R Q ~Q 1 0 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 Q0 ~Q0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

19. Edge-triggered D Flip-flop 1 1 0 1 1 0

20. Edge-triggered D Flip-flop 1 1 0 1 1 0 1 0

21. Edge-triggered D Flip-flop 1 1 0 1 1 0 0 1

22. Edge-triggered D Flip-flop 0 1 1 0 1 0 0 1

23. Edge-triggered D Flip-flop 0 0 1 1 0 1 0 1

24. Edge-triggered D Flip-flop 0 0 1 1 0 1 1 1

25. Edge-triggered D Flip-flop 1 0 1 0 1 1 1 0

26. Edge-triggered D Flip-flop

27. Edge-triggered D Flip-flop

28. Edge-triggered D Flip-flop with asynchronous set and reset 1 1 0 1 1 0

29. Edge-triggered D Flip-flop with asynchronous set and reset 1 0 1 1 0 1 0 1 1 0

30. Edge-triggered D Flip-flop with asynchronous set and reset 1 1 1 1 0 1 0 1 1 0

31. Edge-triggered D Flip-flop with asynchronous set and reset 0 1 0 1 0 1 1 1 0 1

32. Edge-triggered D Flip-flop with asynchronous set and reset 1 1 0 1 0 1 1 1 1 0

33. Edge-triggered D Flip-flop with asynchronous set and reset

34. D CLK Q ~Q 0 0 1 1 1 0 X 0 Q0 ~Q0 D Flip-Flop Positive edge triggered D gets latched to Q on the rising edge of the clock.

35. Controlled inverter Each Xilinx 95108 macrocell contains a D flip-flop

36. Each Xilinx 95108 macrocell contains a D flip-flop Note asynchronous preset x z y Note asynchronous reset

37. Divide-by-2 Counter CLK D D Q Q0 CLK ~Q ~Q0 Q0 D = ~Q0 D = ~Q0

38. div2cnt.abl module div2cnt ( Q ,clr ,clk ); input clr ; wire clr ; input clk ; wire clk ; output Q ; reg Q ; wire D ; assign D = ~Q; // D Flip-flop always @(posedge clk orposedge clr) if(clr == 1) Q = 0; else Q = D; endmodule D D Q Q0 CLK !Q ~Q0 D = ~Q0

39. J-K Flip-flops J K D 0 0 Q 0 1 0 1 0 1 1 1 ~Q D = J & ~Q | ~K & Q

40. J-K Flip-flops

41. T Flip-flops T D 0 Q 1 ~Q D = T ^ Q

42. T Flip-flops