ALU Organization Michael Vong Louis Young Rongli Zhu Dan

1. ALU OrganizationMichael VongLouis YoungRongli ZhuDan

2. Overall ALU Organization • The output lines (Y3 … Y0) run all the way through

3. ALU Organization:One Function Per Column Control signals will enable all transmission gates in a column

4. ALU Organization:One Bit Per Row Only one transmission gate in a row will be turned on. Only one function will drive Y.

5. Adder Logic Design

6. BK Cell States • Our adder uses BK Cells. • For each column of addition, there are three possible states. (0 + 1) or (1 + 0) is carry propagate = P (1 + 1) is carry generate = G (0 + 0) is carry kill = K 0 1 0 + 1 1 0

7. BK Cell Truth Table Each BK cell looks at the carry status of two networks and generate a single carry status.

8. BK Cell Boolean Equation • Note: • The encoding used: G = 11, K = 00, and P = 10 or 01 • Y1 and Y0 are the same Boolean function. Just do the layout for Y1 and replicate it twice to get a BK cell • This is the same function as the ripple adder’s carry out • Y1 = BD + AD + AB • Y0 = BC + AC + AB

9. Using BK Cells to make an Adder • There is only one rule to using BK cells: To compute the carry of Ci, you must have enough BK cells to reach all preceding bits, from bit (i-1) to bit 0. • You can have just enough BK cells to compute the final carry, or you can have lots of BK cells to compute all carries.

10. BK Cell Example(part 1 of 2) If you just want the carry out of an 8 bit addition operation, then you will need 7 BK cells.

11. BK Cell Example(part 2 of 2) • Note that the first input into the first BK cell on the right (the C and D of the red box), must be either G (11) or K (00). Let say the number we are adding are called A and B, this input is C = D = A0Bin + A0Cin + B0Cin . • The final output, the Y1 and Y0 of the yellow box, is also either G(11) or K(00).

12. Our Adder’s BK Cells This adder is around the same speed as a ripple adder. The entry into the red cell has the same delay as a BK cell. Red cell’s C = D = A0B0 + A0Cin + B0Cin . So from input to C3 there are really 3 BK stages. Each stage is the same as a carry out of a ripple.

13. Other BK Cell Examples Our adder does not benefit from the BK cells because it’s only 4 bits wide. Larger adders do benefit. Sklanski's adder: Problem: high fan-out for the lowest C8 BK cell. Screen shots are taken from: http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Additi.htm

14. Another BK Cell Example Kogge & Stone adders: This one has more BK cells but less fan-out.

15. Our Adder --- After the BK Tree • After the carries are generated, add them to the xor sums. • If we are add A and B, and let the answer be SUM: SUM0 = (A0 xor B0) xor C0 SUM1 = (A1 xor B1) xor C1 SUM2 = (A2 xor B2) xor C2 SUM3 = (A3 xor B3) xor C3 This operation of two xor gates is called the “summer” in our adder.

16. Summer Schematic Y = (A XOR B) XOR C The idea is to have A and B preset a path so that when C is correctly set, it will show up at Y really fast. It didn’t work out that well.

17. Adder Logic Summary • A tree of BK cells are used to compute all of the carries. • The final sum for the i-th bit is Ai xor Bi xor Ci , where A and B are the numbers that we are adding, and C is the carry computed by the BK cells.

18. Confirming the Logic with Verilog module bk(Y1, Y0, A, B, C, D); input A, B, C, D; output Y1, Y0; assign Y1 = (B&D) | (A&D) | (A&B); assign Y0 = (B&C) | (A&C) | (A&B); endmodule module summer(Y, A, B, C); input A, B, C; output Y; assign Y = (~A & ~B & C) | (~A & B & ~C) | (A & ~B & ~C) | (A & B & C); endmodule

19. adder.v (page 1) module adder(SUM, COUT, A, B, CIN); input [3:0] A, B; input CIN; output [3:0] SUM; output COUT; wire c1, c2, c3, c4; assign c1 = (A[0] & B[0]) | (A[0] & CIN) | (B[0] & CIN); wire bk1_0, bk1_1, bk2_0, bk2_1; wire bk3_0, bk3_1, bk4_0, bk_1; bk bk1(bk1_1, bk1_0, A[1], B[1], c1, c1); bk bk2(bk2_1, bk2_0, A[2], B[2], bk1_1, bk1_0); bk bk3(bk3_1, bk3_0, A[3], B[3], A[2], B[2]); bk bk4(bk4_1, bk4_0, bk3_1, bk3_0, bk1_1, bk1_0);

20. adder.v (page 2) assign c4 = bk4_1; assign c3 = bk2_1; assign c2 = bk1_1; assign COUT = c4; summer s0(SUM[0], A[0], B[0], CIN); summer s1(SUM[1], A[1], B[1], c1); summer s2(SUM[2], A[2], B[2], c2); summer s3(SUM[3], A[3], B[3], c3); endmodule

21. test.v module testbench; wire [3:0] SUM; wire COUT; reg [3:0] A, B; reg CIN; adder adder1(SUM, COUT, A, B, CIN); reg [4:0] i, j, k; initial begin CIN = 4'd1; for(i = 0; i < 16; i = i + 1) begin for(j = 0; j < 16; j = j + 1) begin A[3:0] = i[3:0]; B[3:0] = j[3:0]; #20; k = i + j + 1;

22. test.v (page 2) if(SUM[3:0] != k[3:0]) begin $display("At time %t, A = %d, B = %d, CIN = %d, SUM = %d, COUT = %d \n", $time, A, B, CIN, SUM, COUT); end else begin $display("A = %d, B = %d, CIN = %d tested \n", A, B, CIN); end end end $display("end of test \n"); end endmodule

23. Simulation with ModelSim

24. Adder Circuitry

25. Layout Guidelines Transistor Sizes (most of the time): PMOS: L = 0.6 um, W = 5.4 um NMOS: L = 0.6 um, W = 3 um Cell height: Total Height: 27 um VDD and GND path width: 1.5 um

26. Cell Hierarchy • zproj_adder4b • zproj_bk • zproj_bk_y1 • zproj_summer • Zproj_mux2b

27. The bk_y1 Cell AOI Schematic Recall that the BK cell has a Y1 and Y0

28. The bk_y1 layout Note that metal 2 can route vertically through almost all of the cell.

29. The Complete BK Cell Schematic

30. The bk Cell Layout View 1

31. The bk Cell Layout View 2 A and B is the same all the way across while C and D swap rows Y1 is in the middle while Y0 is at the far right

32. Multiplexer Schematic The multiplexer is the basic cell for the summer

33. Multiplexer Schematic

34. Multiplexer Layout Note that vertical routing of metal 2 is possible in less than half of the cell.

35. Multiplexer Test Setup Note how ideal sources are fed directly into the mux

36. Multiplexer Power Usage

37. Multiplexer Test Result The load capacitance is 30 fF

38. Multiplexer Test Results (Page 2) Power = 14.95 W/cm2 The first group of results highlighted in red cells turned out to be inaccurate. The ONE and ZERO lines are not gate terminals. When the path way is set (S held steady), the rate at which the output changes is actually proportional to the change in input. The output is changing rapidly in the test because the input is an ideal voltage source with a rise time of 200 ps. A more realistic switching time can be obtained by passing the ideal input through two inverters before sending it to the “ONE” or “ZERO” line of the multiplexer.

39. Summer Schematic

40. Summer Layout View 1 The (NOT C) is labeled as C’

41. Summer Layout View 2 The right most Y is the sum

42. Putting the Support Cells Together to Form a 4 Bit Adder

43. Adder Schematic Page 1 This is the BK tree part of the adder

44. Adder Schematic Page 2 Output from the BK tree, and the original A and B bits are passed into the summer cells.

45. Adder Layout Adder Layout Note the long distance metal2 vertical routing

46. Adder Layout View 2

47. Adder LayoutInput View

48. Adder Layout Output View

49. Adder Layout Area

50. Adder Test Setup Each output pin is loaded with 30 fF capacitors. 1 1 1 1 0 0 0 1 0 I used VDC for 1 and VPULSE for 0.