CAD Techniques for IP-Based and System-On-Chip Designs

1. CAD Techniques for IP-Based and System-On-Chip Designs Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {Email: chunghaw@cs.nthu.edu.tw}

2. Outline • Introduction • Basic synthesis tasks • Codesign of embedded systems • FPGA synthesis and rapid prototyping • IP-reuse design methodologies • System-on-chip design methodologies • HDL-based layout synthesis methodologies

3. Computer-Aided Design (CAD) • Why? • What? • How?

4. Human-Centric Design Methodologies • Designers are the creator of designs. • Designers are artists. • Designers pursuit the state of arts. • Free styles with less discipline. • May not be efficient on handling complex designs. • May not be effective on shortening the design cycle.

5. Human Vs. Computer (Automation) • Human is good at innovating creation. • Human is not good at handling tedious and repetitive tasks. • Computer is good at handling tedious and repetitive tasks, at least it will never complain about it.

6. Why needs CAD? • Design is getting more and more complex. • Try to develop an error-prone design? • Time-to-market pressure.

7. What is CAD? • CAD = Computer-Aided Design. • CAD will never be in the leading role of a design process!!! Just a supporting role. • Any techniques, methods, solutions which are used solve a problem in a design process.

8. How to apply CAD? • Understand the design process. • Identify the problems which need CAD supports. • Correctly define the problem and then solve it.

9. Idea System Hardware Software OS Chips Application SW System board A Typical System Design Process

10. Chip spec. RTL design Logic design Gate-level design Layout A Typical Chip Design Process

11. Silicon Compilation • Compiler: converting a high-level source code to a object code. • Silicon compiler: converting a high-level source code (system/chip description) to a piece of silicon.

12. Synthesis • Synthesis is a process which converts a design from one domain to another • System-level synthesis • High-level (Behavioral) synthesis • RTL synthesis • Logic synthesis • Layout synthesis • HDL-based synthesis

13. The Y Chart Behavioral Structure System level CPU,Mem System spec. Ckt level Transformation (Synthesis) Chip/Board Physical

14. Design Level Behavioral Structure Physical CPU, Mem. Processor ALU, Reg. Etc., Gate, FFs Transistor Chip/board Block/chip Macro-cell Std. Cell Polygon System Spec. Algorithm RTL spec. Boolean Eqn. Differential Eqn.

15. Transitions in the Y Chart Behavioral Structure Synthesis Optimization Analysis Refinement Abstraction Generation Extraction Physical

16. System-Level Synthesis • Inputs: Design functionality (e.g., instruction of a computer) and a set of design constraints or requirements. • The transition from a system-level specification to one or more subsystem descriptions at the algorithmic level (a set of communicating concurrent processes, together with a behavioral description at the algorithmic level for each subsystem).

17. High-Level Synthesis • Starting point: a behavioral description at the algorithmic level, which defines a precise procedure for the computational solution of a problem. No notion of “CLOCK”. • Outputs: controller and datapath. • Time/area tradeoff.

18. RTL-Level Synthesis • Inputs: an RTL netlist and a set of design constraints. • Each component in the netlist is described either in behavioral, structural, or logic level. • Controller synthesis: the transition from controller behavior to structure. • Module generation.

19. Logic-Level Synthesis • Inputs: Boolean functions and FSMs. • Outputs: the blocks of combinational logic and storage elements. • Logic minimization and optimization. • Technology mapping.

20. Physical-Level Synthesis • Inputs: a hierarchical gate-level netlist which may contain hard macros and flexible soft macros. • Outputs: a layout. • Floorplanning. • Placement. • Routing. • Compaction.

21. HDL-Based Synthesis • Why? What? How? • VHDL and Verilog: originally a simulation-based language. • Programming languages => hardware! • Syntax and semantics gaps. • Compilation is the key to the HDL-based synthesis.

22. Other Design Issues • Design entry. • Design verification and validation: - simulation - formal method - logic emulation - rapid prototyping - design rule checking • Testing

23. Basic Synthesis Tasks

24. The Specification Language Problem • Many Hardware Descriptive Languages (HDLs): VHDL, Verilog, AHPL, ISP, PMS which are derived from general programming languages, e.g., ADA, ALGOL, C, and PASCAL. • All general programming languages can be used for system-level simulation at behavioral-level. • No single language can cover the software and hardware spectrum!!!! • CASE problem!!!

25. Behavioral Transformations • Optimizing transformations: - Procedure in-line expansion - Loop unrolling - SELECT (IF & CASE) transformations • Processes: concurrent execution. • Interprocess communication: synchronization issues • Similar to OS problem!

26. Communications • Mapping the logical communication structure onto a physical communication structure. • Synthesis of communication protocols.

27. System-Level Partitioning • Hardware-software codesign. • A lot of academia studies in this area!!! • The key to the success is an accurate estimation engine to support the partitioning procedure!!!

28. Design Exploration • Time/area tradeoff. • Architectural-level exploration. • Memory hierarchy and organization. • System-level early design planning. • Design estimation issues.

29. The Classical High-Level Synthesis Tasks • Design representation issues. • Behavioral transformations. • Allocations. • Scheduling. • Binding. • Estimation and design exploration. • Why after a decade of intensive research effort high-level synthesis has not yet been accepted by industry????