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Integration with ATLAS DAQ

Integration with ATLAS DAQ. Marcin Byszewski. Outline. FEC zero suppression Integration with ATLAS DAQ. FEC zero suppression. APV25 analogue, 128 channels * number of time samples FEC FPGA firmware module by R. Giordano and S. Martoiu

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Integration with ATLAS DAQ

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  1. Integration with ATLAS DAQ Marcin Byszewski Marcin Byszewski, CERN

  2. Outline • FEC zero suppression • Integration with ATLAS DAQ Marcin Byszewski, CERN

  3. FEC zero suppression • APV25 • analogue, 128 channels * number of time samples • FEC FPGA firmware module • by R. Giordano and S. Martoiu • Possibility to bypass for a single APV25 chip (configure stages) • Configuration (pedestal measurement) must be run by user • Passed first tests with the mmDAQ • Remotely controlled by DCS (by G. Iakovidis) • Finishing debugging stage • Max rate not tested • Limits number of time bins to ~16 Marcin Byszewski, CERN

  4. FEC zero suppression • Based od mmDAQ ZS • Suppression cut: Qsum / Ntime_bins<Pedstddev * A Qsum = sum of charge Ntime_bins = number of time samples Pedstddev = Pedestal std.dev. A = user defined factor (about 0.8 in mmDAQ) APV signal time Marcin Byszewski, CERN

  5. FEC zero suppression • Data Format: typedef char BYTE; // 8-bit word typedef unsigned int WORD32; // 32-bit word typedef unsigned short int WORD16; // 16-bit word struct APV_HEADER { BYTE APV_ID; // APV Identifier number on the FEC card (0 to 15) BYTE N_CHANNELS; // the number of channels which will be following the header BYTE N_SAMPLES; // the number of samples per channel BYTE ZS_ERROR; // Error code from the Zero Suppression Block, meaning have to be defined WORD32 RESERVED; // 32 bits reserved for future use }; struct CHAN_INFO { BYTE RESERVED; // 8-bits reserved for future use BYTE CHAN_ID; // Channel identifier, 0 – 127, future: 128 common mode , 129 for error codes WORD16 CHANDATA[N_SAMPLES]; // 16 bit words, actual data will be 13-bits wide }; Marcin Byszewski, CERN

  6. Micromegas in ATLAS @ winter shutdown • Plan to install during this Xmas shutdown: • 8x9 cm MBT0 chamber on the edge of MBTS • 1.2x0.5m2 test chamber (4 active planes, X+U strips) • HW • All equipped with APV25 chips (4 + 4*10 = 44 chips) • 25 m HDMI cables (to be tested,@ 5V) • 4-5 FECs • DTC links to 1 SRU unit • Optical S-Link fibre to a ROS in USA15 cavern Marcin Byszewski, CERN

  7. Current MAMMA’s Lab setup Trigger HDMI 16x APV25 Ethernet mmDAQ ZS SRS DCS FEC Raw data out DCS Marcin Byszewski, CERN

  8. Integration into ATLAS DAQ Trigger 16x APV25 HDMI mmDAQ ZS FEC Raw data out HDMI 44 APV25 FEC SRU ATLAS ROS DTC optical FEC FEC FEC Data out LVL1 Accept LVL1 Accept Ethernet DCS Marcin Byszewski, CERN

  9. Integration Challenge 1: FPGA FW Missing FPGA firmware Enormous software development effort on a short time scale @LMU, Napoli, CERN HDMI 44 APV25 FEC SRU ATLAS ROS DCS ZS DTC optical FEC FEC DTC FEC DTC S-Link Data out Event builder LVL1 Accept LVL1 Accept Ethernet DCS Raffaele Giordano Andre Zibell Vincenzo Izzo SorinMartoiu Marcin Byszewski, CERN

  10. SRU FW blocks for ATLAS DAQ To FECs SRU L1 trigger TTCrx L1 trigger forwarding On/Off To ROS Event building Read DTC into input buffer S-Link Data out DTC links data data data Slink HW Event data To PC DCS DCS DCS Ethernet Marcin Byszewski, CERN

  11. Integration Challenge 2: Timings Marcin Byszewski, CERN

  12. Integration: Challenge 2 • Synchronous data flow • @75kHz (13us) APV ->FEC readout timing APSP 4x70clocks = 7us / timebin output 140bits*clock = 3500 ns /timebin 16 time bins -> 220us Ok for 1 time sample, but we want to send 16 time samples. Do not provide data for every LVL1 Accept HDMI 44 APV25 FEC SRU ATLAS ROS DCS ZS DTC optical FEC FEC DTC FEC DTC S-Link Data out Event builder TTC LVL1 Accept LVL1 Accept Ethernet DCS Raffaele Giordano Andre Zibell Vincenzo Izzo SorinMartoiu Marcin Byszewski, CERN

  13. LVL1 handling scheme (LVL1 ID5) <- to ROS SRU FEC LV1 ID 1 APV ROS LV1 handler Processing data? NO Set to YES Forward LV1 to FEC Return event to ROS (empty) forward LV1 readout (LVL1 ID1) (LVL1 ID1) time ROS LV1 handler Processing data? YES Store reference Do not forward trigger (LVL1 ID2) Zero suppression (LVL1 ID1) (LVL1 ID1) Build & Store Event Set Processing data to NO +200us (…) ROS LV1 handler Processing data? NO Set to YES Forward LV1 to FEC Return event to ROS (BCID1) (LVL1 ID5) SRU stores references of the incoming LVL1. When finished processing it sends out the processed event and dummy responses to LVL1 received in the mean time. Marcin Byszewski, CERN

  14. Integration: Challenge 2 • Synchronous data flow • @75kHz (13us) APV ->FEC readout timing APSP 4x70clocks = 7us / timebin output 140bits*clock = 3500 ns /timebin 16 time bins -> 220us 160MBit/s HDMI 44 APV25 FEC SRU ATLAS ROS DCS ZS DTC optical FEC FEC DTC FEC DTC S-Link Data out Event builder TTC LVL1 Accept LVL1 Accept Ethernet DCS Raffaele Giordano Andre Zibell Vincenzo Izzo SorinMartoiu Marcin Byszewski, CERN

  15. Summary • progress to prepare for ATLAS DAQ integration this winter 23/11/2011 RD51 Mini week Marcin Byszewski, CERN

  16. Backup slides Marcin Byszewski, CERN

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