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Reconfigurable architectures

Explore the world of static and dynamic configurable systems such as SPYDER, RENCO, FIREFLY, and BioWatch. Learn the differences between static and dynamic configurations, and their applications in enhancing performance and adapting to changing specifications. Discover the advancements in reconfigurable architectures like PipeRench, SPYDER, RENCO, and FIREFLY machines, showcasing speed improvements and application versatility. Dive into the self-repair and self-replication circuits of BioWatch and the innovative capabilities of PipeRench in accelerating numerically intensive applications without redesign. Understand the pipeline reconfiguration concept and hardware virtualization for optimized performance and scalability.

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Reconfigurable architectures

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  1. Reconfigurable architectures ESE 566

  2. Outline • Static and Dynamic Configurable Systems • Static • SPYDER, RENCO • Dynamic • FIREFLY, BIOWATCH • PipeRench: Reconfigurable Architecture and Compiler

  3. Static vs. Dynamic Configurable Systems • Static: • Improves performance for a given task (coprocessor) • Optimize the utilization of the resources (task division) • Dynamic • To adapt to changing/incomplete specifications • Eliminate human design

  4. SPYDER: reconfigurable processor development system • Static (performance) reconfigurable coprocessor • Fixed control unit • Reconfigurable processing unit • Compiler: • Generates FPGA configuration from user-described operators • User writes application

  5. SPYDER architecture

  6. Speed improvement • Conway’s Game of Life • SPYDER, 8MHz: • 115 mill. cells/sec • SPARC, 85MHz: • 6.5 mill. cells/sec

  7. RENCO: reconfigurable network computer • Static (performance) • DOWNLOAD: • Application • Optimal Processor Configuration

  8. RENCO architecture

  9. FIREFLY machine • Dynamic • Evolutionary algorithms <=> evolvable hardware (evolware) • Cellular automata: • Array of cells (1D, 2D, 3D); • Interaction rule: state of one cell determined by neighbors states => rule table

  10. FIREFLY machine (cont’d) • 1-D cell array, 56 cells • 1 cell : D Flip-Flop + combinational logic • Cell n state = f(Cell n-1, Cell n , Cell n+1) • f= reconfigurable

  11. FIREFLY machine: Implementation

  12. Performance • Task: synchronization starting from random configuration • Workstation: 60 configs/s • FIREFLY: 13,000 configs/s @ 1MHz

  13. BioWatch • Embryonic electronics: self repair, self replication circuits • BioWatch: seconds/minutes • Cells: modulo-6, modulo-10 • Gene: subprogram of the cell • Genome: the set of genes • Each cell stores the entire genome, but uses only 1 gene => can replace another cell

  14. Self replication Self repair

  15. PipeRench • Reconfigurable datapath for accelerating numerically intensive applications • Virtualized hardware • Dynamic reconfiguration • Application portability and scalability without redesign or recompilation

  16. Types of RH • FPGAs: bit-level logic functionality (the basic processing elements compute on 1 bit) • word-based architectures: PipeRench (CMU) (basic PE operates on 8 bits) (basic PE is a small ALU) • coarse architectures: RAW (MIT) (basic PE is a MIPS 2000 core)

  17. What is pipeline reconfiguration? • Split application in N pipelined stages • Use one piece of reconfigurable hardware for all N stages • Reconfigure and feedback at each clock cycle (extreme case)

  18. Pipeline reconfiguration

  19. Hardware Virtualization Actual available hardware Instructions currently in hardware Program Instructions paged out

  20. PipeRench architecture

  21. Processing Element Architecture

  22. Speed Improvement @100MHZ

  23. Speed Improvement (cont’d)

  24. Bibliography • E. Sanchez et al., “Static and Dynamic Configurable Systems”, IEEE Transactions on Computers, June 1999, pp. 556- 564 • Seth Copen Goldstein et al., “PipeRench: A Reconfigurable Architecture and Compiler”, IEEE Computer, 2000, pp. 70-76 • H. Schmit et al., “PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology”, IEEE 2002 Custom Integrated Circuits Conference Proc., pp. 5-3-1- 5-3-4

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