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System-Level Living Roadmap

System-Level Living Roadmap. GSRC Annual Symposium September 28 & 29, 2006 Faculty: Kahng, Markov, Orshansky, Sylvester. System-Level Living Roadmap. Only cost-effective technology innovations reach production What are relevant bounds, and how do they evolve?

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System-Level Living Roadmap

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  1. System-Level Living Roadmap GSRC Annual Symposium September 28 & 29, 2006 Faculty: Kahng, Markov, Orshansky, Sylvester

  2. System-Level Living Roadmap • Only cost-effective technology innovations reach production • What are relevant bounds, and how do they evolve? • What are quantified benefits from available technology options? • Beyond-ITRS: what are system implementation roadblocks? • System-level design optimization and scaling • What are the relevant models and metrics for system scaling? • Early analysis tools • Map technology concerns (power, variability, speed, area, …) to system concerns (total cost, availability, …) • Roadmaps • Connect applications to design and process technologies  well-calibrated cost and resource tradeoffs GSRC Annual Symposium

  3. Roadmap of Parametric Yield Estimation and Optimization: TUNES Variability Data Technology / Circuit Data Fmax Variability SER Macromodeling Statistical Clock Skew GSRC Annual Symposium

  4. Power w/ Leakage Leakage Roadmap of Parametric Yield Estimation and Optimization: Block-Level Probabilistic Power-Delay Exploration • Variability greatly impacts leakagepower and parametric yield • Exponential dependency on process • Package often sets power limits • Cooling costs grow rapidly for higher power Cooling/Power Limit Switching Power Number of Parts Minimum Ship Frequency Power Design Spread Slow Fast Max Ship Freq (With Leakage) Max Ship Freq (No Leakage) GSRC Annual Symposium

  5. Roadmap of Parametric Yield Estimation and Optimization: Block-Level Probabilistic Power-Delay Exploration • How much parametric yield loss can be recovered? • DAC-05 Best Paper: Robust LP, second-order conic programming for sizing / dual Vth • Efficient, large-scale parametric yield maximization • Designer chooses sweet spot in power-delay space, trades timing yield for power yield, etc. • E.g., 5% timing yield loss  25% less power GSRC Annual Symposium

  6. Roadmap of Reliability: Impact of Dynamic Reliability Management • TDDB, EM, thermal cycling, NBTI with dynamic stress inputs • PID + threshold control solution • DRM voltage control • Boosts/throttles maximum assignable voltage • +25% peak performance with typical workload/temperature • +12-15% peak performance  workloads • +10-12% peak performance  temperature • Future directions • Parametric performance degradations vs. hard failures • Sensor architecture and placement • ElastIC: A system-level adaptive architecture GSRC Annual Symposium

  7. Roadmap of Reliability: Efficient Soft Error Analysis and Optimization in Combinational Logic • Proposed algorithm considers injection, propagation, and merging of SET descriptors (capturing correlation between transient waveforms and rate distribution function) in STA-like fashion • Waveform models based on Weibull, 1-time characterization cost • Highly efficient: runtime linear with #gates (25K gates in 0.2sec) • Accurate: ~15% error in FIT • vs. Monte-Carlo SPICE • Used in SER optimization • Gate sizing + flip-flopassignment shows 28X SER reduction with nodelay penalty and 5% area overhead • Runtime: 1 minfor 5K gates GSRC Annual Symposium

  8. Roadmap of Reliability: Bottom-Up Reliability Prediction • System-level analysis requires: • Precise gate electrical properties • Logical structure of the circuit • System-level timing behavior •  Electrical, logical, and timing window masking • Cell library characterization • Intractability (#P) of logical masking • Pioneered use of decision diagrams in this context • DATE-05 Best Paper award • Three new static SER analysis tools • Pulse Generation: • Library: Output Waveform = f(Collected Charge) Vth Y 0 PW CL A=0 B=1 • Pulse Propagation: • Library: Output Waveform = f(Input Waveform) Y Vth Vth A CL 0 PWin B=1 GSRC Annual Symposium

  9. Fast analytical modeling and computational technique for logic SER analysis for cell level designs Excellent accuracy compared to SPICE Best Paper Award, ISQED 2006 Roadmap of Reliability: Fast Analysis of Soft Error Susceptibility (FASER) for Cell-Based Designs GSRC Annual Symposium

  10. Roadmap of Reliability: System Susceptibility to Soft Errors: Memory Modeling • Memory arrays much more sensitive to single event upsets • Developed first analytical model for predicting SER noise margins under dynamic disturbances (single event upsets) GSRC Annual Symposium

  11. Roadmap of Reliability: Synthesis for Reliability and Probabilistic Testing • Optimize reliability usingrecent competitive synthesis frameworks • Allow or veto logic transformations • Using ABC from Berkeley • Probabilistic test • Take deterministic patterns • Compute multiplicitiesusing a reliability evaluator • Evaluating 4 GSRC reliability evaluatorsand two more • Figure out which work ! • Use in estimation • Use in synthesis and optimization • Use in circuit test New project withAir Force Research Lab GSRC Annual Symposium

  12. Roadmap of Power and Variability: Energy-Optimal Gate Sizing for Subthreshold Circuits • Subthreshold energy efficiency is limited by leakage • Energy optimal supply voltage, Vmin, determined by rise in leakage • At Vmin, leakage accounts for ~30% of total energy • Increasing gate sizes along critical paths can reduce energy • Shorter clock period = shorter leakage time • A reduction in leakage affects the location of Vmin; therefore, Vdd can be reduced if leakage is reduced • An energy-driven, TILOS-like sizing algorithm yields energy savings of ~6-15% on ISCAS85 benchmarks 15% energy reduction 6% energy reduction GSRC Annual Symposium

  13. Roadmap of Power and Variability: Design Assessment under Realistically Available Uncertainty Descriptions • In practice, detailed process characterization data for current and future generations are not available • Only partial probabilistic descriptions are accessible, e.g., mean and variance • Timing, power, and parametric yield estimates are affected • Probabilistically-enhanced interval analysis • Use mean, variance, and intervals of circuit parameters to estimate probabilistic bounds for timing and power • Probability box: bounds for cumulative distribution function GSRC Annual Symposium

  14. Roadmap of Power and Variability: Intra-Gate Biasing • Exploit edge effects in modern MOSFET devices that lead to different Ion/Ioff current densities based on position in channel • Key: lengthen channel near edges to suppress high leakage there, reduce Ldrawn in center slightly to compensate • FREE circuit-level leakage reduction on the order of 5-6% • No delay penalty or optimization cost • An orthogonal knob to all other circuit optimization techniques GSRC Annual Symposium

  15. Roadmap of Cost: Low-Volume Implementation • What can be recovered along cost trajectory of Moore’s Law? • OPC, reticle plan, multi-layer reticle strategy, multi-flow production strategy, wafer shot map, blading, mask write and inspect, dicing plan, … many optimization opportunities • Goal: 10X reduction in per-die cost for low volume GSRC Annual Symposium

  16. Die 1 Lay 3 Die 2 Lay 3 Die 1 Lay 2 Die 2 Lay 2 Die 1 Lay 1 Die 2 Lay 1 MFMLMP Reticles • A reticle has multi-layers of multi-projects of multi-flows • Different printing frames for different wafers • More design challenges: layer assignment, flow embedding and frame floorplan Die 1 Lay 3 Die 2 Lay 3 Die 1 Lay 3 Die 2 Lay 3 Reticle 1 Die 1 Lay 2 Die 2 Lay 2 Frame Die 1 Lay 1 Die 2 Lay 1 Die 1 Lay 1 Die 2 Lay 1 Die 1 Die 2 Die 1 Die 2 Reticle 2 Wafer 1 Wafer 2 Example of MFMLMP Reticles: Layer 2 of Die 1 and Die 2 cannot share the same reticle GSRC Annual Symposium

  17. GSRC On-Line MFMLMPR Designer • Flexible: Handles all known practical design constraints • Fast: Interactive solver to minimize manufacturing costs • Graphical viewing of output • Co-developed with, used at Cypress Semiconductor for MFMLMP Reticle design Define Parameters Input Data Output GSRC Annual Symposium

  18. Roadmap for Physical Implementation QOR • Delay, Power: large part in interconnect • Growing problem with every technology node • Spatial embedding becomes more critical • Unpleasant surprises at first spatial embedding(industry: many RTL designs are found infeasible) • Early planning for distances, shapes and sizes • Manual planning has hit the complexity limit • System must co-evolve with its spatial embedding • Embedded memories, IPs, analog/RF, … • Vertically-consistent spatial embedding • Consistent objectives and optimizations through multiple levels of abstraction • Smooth transitions between design steps, with gradual refinement • Support for design optimizations such as high-level and RTL synthesis GSRC Annual Symposium

  19. Vertical Consistency (1) • SCAMPI: SCalable Advanced Macro Placement Improvements • Variety of macro sizes & shapes • Look-ahead, macro clustering,obstacle evasion • Floorist:Floorplan Assistant(constraint-driven FP repair) red: overlap blue: block movement (no overlap) GSRC Annual Symposium

  20. Vertical Consistency (2) • Physically safe logic restructuring • Top-down whitespace & buffer area allocation • Support for design optimizationsvia selective re-embedding (below) • More direct optimization of routed net lengths (ROOSTER), at several design steps Legalize Improve GSRC Annual Symposium

  21. SLLR Theme Posters • Parametric Yield Estimation and Optimization • Eric Karl, Dennis Sylvester and David Blaauw: Multi-Mechanism Reliability Modeling and Management in Dynamic Microprocessor-Based Systems • Scott Hanson, Dennis Sylvester and David Blaauw: A New Technique For Jointly Optimizing Gate Sizing and Supply Voltage in Ultra-Low Energy Circuits • Saumil Shah, Dennis Sylvester, Andrew Kahng and Youngmin Kim: Intra-Gate Channel Length Biasing for Transistor-Level Circuit Optimization • Roadmap of Reliability • Bin Zhang and Michael Orshansky: Evaluating Reliability of On-Chip SRAM Arrays using Dynamic Stability Analysis • Rajeev Rao, Vivek Joshi, David Blaauw and Dennis Sylvester: Efficient Soft Error Rate Computation and Circuit Optimization Techniques to Mitigate Soft Errors in Combinational Logic • Wei-Shen Wang and Michael Orshansky: Yield Estimation under Realistic Descriptions of Parameter Uncertainty • Roadmap of Cost • Andrew Kahng and Xu Xu: A General Framework for Multi-Flow Multi-Layer Multi-Project Reticle Design • Roadmap of Physical Implementation QOR • Jarrod Roy and Igor Markov: Vertically-Consistent Spatial Embedding of Integrated Circuits and Systems • Roadmap of Power and Variability • Andrew Kahng, Swamy Muddu and Chul-Hong Park: A Scalable Auxiliary Pattern-Based OPC Strategy for Better Printability, Timing and Leakage Control • Andrew Kahng and Swamy Muddu: Design-Centric Modeling and Optimization of BEOL Interconnect Stacks • Andrew Kahng, Kambiz Samadi and Puneet Sharma: Study of Floating Fill on Interconnect Capacitance • Andrew Kahng and Kambiz Samadi: Nanometer Era CMP Fill for Variability Reduction • Andrew Kahng and Puneet Sharma: CMP Fill for Reduced STI Variability • Andrew Kahng and Swamy Muddu: Predictive Modeling of Systematic Intra-die Variability • Andrew Kahng and Rasit Topaloglu: Interconnect Optimization through Design Rule Generation GSRC Annual Symposium

  22. Toward System Scaling Theory Future Scaling • Driven by system constraints • Non-determinism: size impact mediated by power density, redundancy overhead, low yield, increased comm overhead • System-leveloverdesign and effective transistor density • Performance is achieved by multi-core architectures running at lower frequencies • Adaptivity/reliability  many transistors are used to diagnose and tune • Power trades off with design time • Impacts of concurrency, spatial embedding, application domain, … Traditional Scaling • Driven by min feature size • Determinism: size directly impacts performance and density • FO4-based performance metric • Transistors are either logic or memory • Cost not discussed (e.g., design TAT, leakage current from Tox scaling, …) GSRC Annual Symposium

  23. Future: GSRC Modeling and Metrics SIG • Enable system design to comprehend impact and feasibility of technology options • Variability, power, cost • Reliability, flexibility, resilience • Initial focus: uncalibrated, “variational” scaling models • Priority: modeling requests from system-level design and GSRC sponsors • “X% increase in reliability requires Y% increase in power”? • “X% (transient + hard) fault coverage can be achieved with < Y% area overhead”? • How to measure efficiency and yield in the presence of failures? • Approximations + Abstractions  “block models” for system optimization • Future system scaling is dominated by silicon non-idealities • Variability and reliability will fundamentally change density, power, speed, cost scaling laws • Long-term goal: a new system scaling theory GSRC Annual Symposium

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