CRKit R4 BFM Simulation

1. CRKit R4 BFM Simulation WINLAB – Rutgers University Date : June 16, 2011

2. Bus Functional Simulation • Enables verification of hardware components connected to a bus (Ex: PLB, OPB) • Involves • Bus Functional Models(BFMs) – hardware components (provided as hdl files) that model a bus interface. • Bus Functional Language(BFL) – high level language to describe the behavior of a BFM. User can create a .bfl file which describes the required bus transactions. • Bus Functional Compiler(BFC) – Software that translates BFL code to commands that actually program a BFM. • IBM CoreConnect Toolkit – provides tools for simulation of PLB, OPB and DCR systems

3. IBM CoreConnect PLB Toolkit BFMs • PLB Master • PLB Slave • PLB Monitor - samples all PLB signals in every clock cycle and checks for violations of the PLB architectural specification during simulation. Reports error, warning conditions to the user with a display message. • PLB Core/Arbiter • BFM Synchronization Bus - inter-communication bus for event and transaction synchronization among the models, consists of non- PLB I/O signals or signals used for testing purpose. Ex: Processor interrupt, Simulation start pulse

4. BFM System

5. BFM System Simulation Methods • IBM CoreConnect Toolkit • HDL files for predefined systems that include bus, master, slave, monitor. • Modify the predefined systems to manually connect and test the required hardware components. • XPS BFM Package • BFMs tailored to be used in XPS – IP cores. • BFM system to test your IP can be generated via ‘create/import peripheral’ wizard.

6. Generating BFM System using XPS (1/2) Install BFM package Generate simulation platform (xps project) by selecting an option in the create/import peripheral wizard while importing your IP to XPS. Generate simulation HDL files (GUI–Simulation Tab)

7. Generating BFM System using XPS (2/2) • Important Files generated @<xps_proj>/pcores/xxx/devl/bfmsim • bfm_system.mhs • /simulation/behavioral/bfm_system.vhd – top level • /simulation/behavioral/my_core_wrapper.vhd – instantiates xxx_tb (xxx is the IP you import) • /pcores/xxx_tb/simhdl/vhdl/xxx_tb.vhd – instantiates the DUT (your IP xxx) and has logic to send stimulus to user I/O other than PLB signals and to process synch. signals. • /simulation/behavioral/bfm_system.do -- compiles all the vhdl files required for simulation • /scripts/sample.bfl • /scripts/run.do • bfm_sim_cmd.make

8. CRKit System

9. BFM simulation of CRKit System (1/4)

10. BFM simulation of CR Kit System (2/4) • Unzip xps project at crkit_svn\design\trunk\pcore\R4 locally • Move *.vhd from <xps_proj>/pcores/xxx/devl/bfmsim to crkit_svn\design\trunk\bfm\R4\src • Move <xps_proj>/pcores/xxx/devl/bfmsim/pcores/xxx_tb/simhdl/vhdl/xxx_tb.vhd to crkit_svn\design\trunk\bfm\R4\src

11. BFM simulation of CR Kit System (3/4) • Modify xxx_tb.vhd • instantiate tb_top as DUT • add synch. Logic • add generic test_case_no • Modify my_core_wrapper.vhd – add generic test_case_no • Modify bfm_system.vhd – add generic test_case_no • Design/trunk/tb/R4/tb_top.vhd - instantiate cr_top_app + phy, eth_drv, sim_mgr – generic test_case_no

12. BFM simulation of CR Kit System (4/4)