ASIC, Customer-Owned Tooling, and Processor Design

1. ASIC, Customer-Owned Tooling, and Processor Design Design Style Myths That Lead EDA Astray Nancy Nettleton Manager, VLSI ASIC Device Engineering April 2000

2. Design Style Myths • COT is a design style that achieves higher performance through greater ownership of physical design. • ASICs are slower than processors because of design margin. • Design automation tactics tuned on processors are effective on ASICs if they are more heavily automated.

3. Synthesis Synthesis Synthesis Synthesis Placement Floorplan Floorplan Floorplan Routing Placement Placement Placement Timing Closure Timing Closure Routing Routing Routing Xcap Closure COT? COT? Evolution of the ASIC Design Flow Early 90’s 0.6um-1.0um Mid-90’s 0.35um-0.5um Late 90’s 018um-0.25um Today <=0.15um Customer ASICSupplier

4. Customer ASICSupplier Wafer Yield Final Test Yield Package/ Assembly/ Test Tested Parts Physical Design Logical Design Fab Netlist + Timing Constraints GDSII Customer Foundry Pkg/Test Difference Between ASIC & COT • ASIC model: ASIC supplier responsible for physical design, silicon fabrication, & package/assembly/test. • COT model: Customer responsible for physical design, wafer, and final test yield.

5. Meaning of Customer-Owned Tooling Has Changed • Used to mean who owned physical design, the foundry or the customer. • Now it means who is responsible for the supply chain, regardless of the design flow used. • The term Customer-Owned Tooling • No longer defines a design flow. • Transfer of silicon responsibility from a vertically integrated ASIC supplier to the customer (with commensurate cost reduction).

6. ASIC Model COT Model ASIC Supplier Foundry ASIC Supplier Customer Implications of Yield Ownership Two Types of Yield Was the wafer processed correctly? Was the design properly targeted within process distribution? • Physical design determines target within a process distribution. • Clock • Power • Signal Integrity • Performance Verification

7. Yield and Performance • ASICs target full yield at target performance. • Clock rate often defined by system interface • No value in running faster. • Non-functional if slower. • Processors typically do not target full yield at target performance. • Marketable at many performance points. • Added value for higher performance parts, even if yield is limited. • Can still sell slower parts.

8. Most Like ASIC Custom Circuit Design Memory Design Datapath Mapping Synthesis Place & Route Custom Layout Datapath Compilation Custom Layout Chip Integration Microprocessor Design Flow Overview RTL Reduced Emphasis on Synth’d Logic UltraSparcI/II 20+% UltrasparcIII 15% Next Gen Sparc 5%

9. ASIC Processor Synthesized Logic Memory Datapath Custom Circuit Design Key Differences in Design Content • Dominated by synthesized logic • Dominated by custom circuit design. • Compiled memories embedded in logic. • Custom memories as independent blocks. • Lightly partitioned. • Heavily partitioned.

10. Timing Sign-off Delay Calculation Circuit Simulation Timing Closure Automated Manual Power & Clock Synthesized Custom Block Size 100’s of K gates 10’s of K gates Noise Analysis Modeled Simulated Noise Repair Automated Manual Key Methodology Differences ASIC Processor

11. Customer ASICSupplier Package/ Assembly/ Test Physical Logical Fab ASIC Package/ Assembly/ Test Physical Logical Fab COT Foundry Customer Pkg/Test Migrating to COT More Custom Tuning? Not Necessarily. . .

12. If Customer Owns Physical Design, Why Not Tune It? • ASIC content is fundamentally different than processor content. • Volatile system IP is partitioned onto ASICs • Highly tuned system interfaces • Definition evolves right up to system power-on. • Rapid silicon implementation is often more important than detailed tuning. • Even if customer owns physical design, the nature of the system IP may prohibit design tuning. • Then why go COT? $ $ $ $ $ $ $ $ $ $

13. Different Design Objectives • Processor • System chips • More stable architecture (through partitioning) • Achieve best possible timing on limited number of well-understood critical paths. • Less stable architecture (because of system partitioning) • Achieve acceptable timing on large number of unknown critical paths.

14. Implications • Processors becoming increasingly unsuitable as proving grounds for prevalent silicon design techniques. • Excellent vehicles for circuit design and performance-related problems. • Not representative of system chips • Small, homogeneous synthesized logic blocks • Heavily partitioned and tuned • Less automation.

15. Conclusion • Customer-Owned Tooling is a business model, not a design style. • Ownership of physical design does not equate to higher performance. • Performance of system chips is often defined by IP and schedule, not design techniques. • Heavy partitioning and custom circuit design make processor design increasingly less representative of system chip automation.