Computer Organization Lecture 12

1. Computer OrganizationLecture 12 Branch control Jump control Controller FSM University of Portland School of Engineering

2. ck2 ck3 ck1 ck4 ck5 Datapath and controller Controller Input University of Portland School of Engineering

3. Datapath timing overview • Clocks vary from 3 – 5 • Clocks 1 and 2 the same for all instructions • R-type: 2 more • Memory reference • Store: 2 more • Load: 3 more • Branch, Jump: 1 more University of Portland School of Engineering

4. R-type instruction timing Clock Function Register Write Instruction Fetch Instruction Fetch Decode, Reg Read University of Portland School of Engineering

5. 00 00 10 Complete R-type University of Portland School of Engineering

6. Store instruction timing Clock Memory Write Instruction Fetch Instruction Fetch Decode, Reg Read Address Calculation University of Portland School of Engineering

7. 00 00 00 Complete store word University of Portland School of Engineering

8. Load instruction timing Clock Reg Write Memory Read Instruction Fetch Instruction Fetch Decode, Reg Read Address Calculation University of Portland School of Engineering

9. 00 00 00 Complete load word University of Portland School of Engineering

10. Branch (beq) execution Clock 3 • Operation • If (A = = B), PC = ALUout • ALUout = branch address from clock 2 • Functional units • ALU must sub, A-B • ALUout contains optimistic branch address • Zero flag controls write to PC University of Portland School of Engineering

11. Control for branch (beq)? University of Portland School of Engineering

12. 01 00 00 Complete beq University of Portland School of Engineering

13. Beq Instruction Timing Clock ALU Subtract Instruction Fetch Instruction Fetch Decode, Reg Read University of Portland School of Engineering

14. Jump execution Clock 3 • Operation • PC = PC[31-28] || (IR[25-0]<<2) • PC always written • Functional units • Instruction register • Upper 4 bits of PC University of Portland School of Engineering

15. Control for jump? University of Portland School of Engineering

16. Jump instruction timing Clock Write PC Instruction Fetch Instruction Fetch Decode, Reg Read University of Portland School of Engineering

17. 00 00 Complete jump University of Portland School of Engineering

18. Controller and datapath Outputs Outputs Inputs IR(31:25) University of Portland School of Engineering

19. Outputs Inputs NS Decoder Output Decoder Present State Flip Flops Combo logic ROM MUX Decoder Combo logic ROM MUX FSM architecture University of Portland School of Engineering

20. Ten one-bit outputs University of Portland School of Engineering

21. Three two-bit outputs University of Portland School of Engineering

22. 2 Clk 1-3 Clk State diagram overview All instructions require IF, ID (2 clk’s) University of Portland School of Engineering

23. State diagram notation Current State condition condition Signal1 Previous States Next States Signal2 = 0 condition Signal3 = 00 condition Signals not listed are “don’t cares” University of Portland School of Engineering

24. Full FSM state diagram Inputs:Op Outputs: 13 signals States: 10 University of Portland School of Engineering

25. Add state diagram Inputs:Op Outputs: 13 signals States: 10 S0  S1 S6  S7  S0 University of Portland School of Engineering

26. Add instruction timing Clock S0 S1 S6 S7 Add Operands Register Write Instruction Fetch Instruction Fetch Decode, Reg Read University of Portland School of Engineering

27. Find the state transitions? University of Portland School of Engineering

28. University of Portland School of Engineering

29. 01 Control for branch (beq)? Clock 3 Optimistic branch address University of Portland School of Engineering

30. Control for jump? Clock 3 University of Portland School of Engineering

31. Find the state transitions? University of Portland School of Engineering