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Another use of the JTAG Interface on FPGA

Another use of the JTAG Interface on FPGA. Presented by Karin Shusterman. Introduction. JTAG is usually used for testing the board The JTAG interface can be also used to configure FPGAs and program flash devices Can we do more? How about design testing?. Design testing using JTAG.

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Another use of the JTAG Interface on FPGA

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  1. Another use of the JTAG Interface on FPGA Presented by Karin Shusterman

  2. Introduction • JTAG is usually used for testing the board • The JTAG interface can be also used to configure FPGAs and program flash devices • Can we do more? • How about design testing? JTAG Interface as a Communication Port

  3. Design testing using JTAG • The BS technology on FPGA is providing us test and debug capability to our design • We use custom Instructions JTAG controller and to debug the logic of the design • The JTAG controller is already built into the FPGA, minimizing user design JTAG Interface as a Communication Port

  4. Existing solutions • Adding debug outputs and asserts into our design • Using switches and LEDs on board • Using FPGA as a black box • The problem • We can’t know where exactly the problem is • We need many test vectors for many different states • We wish we could have a spy inside our design JTAG Interface as a Communication Port

  5. GNAT • General-purpose Native JTAG Tester • Configured into the FPGA in addition to our design • Uses JTAG controller and resources for debug issues • Allows us to enable communication with our design JTAG Interface as a Communication Port

  6. The uses for GNAT • Replacement for external components (such as LEDs and switches) • Enabling test/diagnostic modes • Reading status/debug registers from design • Controlling a multiplexer to select signals that route to external pins for monitoring • Programming/uploading external memories that interface to the FPGA, such as SDRAM JTAG Interface as a Communication Port

  7. GNAT architecture JTAG Interface as a Communication Port

  8. GNAT component Example with 16 bits • 16-bit USER DR defined • The upper 8 bits of the register are used to control access to the GNAT peripherals • 4 bits identify the peripheral and 4 bits are allocated as an opcode (read/write) • The lower 8 bits are for data communication JTAG Interface as a Communication Port

  9. GNAT peripheral examples JTAG Interface as a Communication Port

  10. Software support Sample script to write to a GNAT peripheral #=========================================================================== # JTAG Chain # ----------------- # Device0 Device1 Device2 # TDI –> 18V02 –> XCV50E –> XC2V4000 -> TDO # # NOTE: binary data is shifted in lsb first #=========================================================================== source $env(XILINX)/chipscope/tcljtag.tcl set handle [jtag_open] jtag_lock $handle jtag_autodetect $handle # Shift the USER2 Instruction (b00011) into the Instruction Register of XC2V4000 jtag_shiftir $handle -buffer "110000" -endstate RTI -device 2 # WRITE: Shift the 16 bit GNAT command into the USER2 Data Register of XC2V4000 # Peripheral: 0x2 # Opcode : 0x0 (write) # Data : 0x34 jtag_shiftdr $handle -buffer "0010110000000100" -endstate RTI -device 2 jtag_unlock $handle JTAG Interface as a Communication Port

  11. JTAG Interface as a Communication Port

  12. JTAG Interface as a Communication Port

  13. Conclusions • We found a way to look into the design using JTAG technology • We are using existing JTAG resources • GNAT • Shows how you can quickly and easily add JTAG debug capability to your design • Has minimal FPGA resource overhead • A simple lightweight and flexible architecture JTAG Interface as a Communication Port

  14. Questions ? JTAG Interface as a Communication Port

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