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Results of 65nm pixel readout chip demonstrator array

Results of 65nm pixel readout chip demonstrator array. Abderrezak Mekkaoui , Maurice Garcia- Sciveres , Dario Gnani amekkaoui@lbl.gov. Objectives. To explore the capabilities of advanced CMOS processes to address future HEP needs (Upgrades, High Luminosity LHC)

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Results of 65nm pixel readout chip demonstrator array

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  1. Results of 65nm pixel readout chip demonstrator array AbderrezakMekkaoui, Maurice Garcia-Sciveres, Dario Gnani amekkaoui@lbl.gov

  2. Objectives • To explore the capabilities of advanced CMOS processes to address future HEP needs (Upgrades, High Luminosity LHC) • Establish an analog front-end baseline • To have a feel of what is the best way these processes should be used in order to maximize benefit • To evaluate radiation hardness

  3. FE-I4 : Front End chip for the IBL • The FE-I4B chip is the production version for IBL installation • Designed in a 130nm CMOS process • Dimensions : 20 mm x 19 mm • Active zone : ~ 90 % of the total area • Respects all the specifications • IBL Production : 1 Module = 1 Chip • The FE-I4 pixel array is organized in Double Columns (DC) • Double Column is divided into 2 × 2 pixel regions • 1 région : 2×2 pixel • Pixel size : 50 x 250 µm² • 26880 pixels • Radiation tolerance > 200 Mrad • Phase I or Phase II • New pixel detector planned • 2 removable internal layers at radii of 3.3–10 cm • 2-3 fixed outer layers at radii of about 15–25 cm • The FE-I4 fits requirements for outer layers in terms of hit occupancy and radiation hardness • A new development (FE-I5) is required for the inner layers 20.2 mm 336×80 pixel array 16.8 mm 2 mm IO pads Periphery Main functional core

  4. Pixel region (2X2) a la FEI4 if implemented in 65nm • Region logic synthesized from FEI4 verilog. • Neither 100% complete nor verified. • Just to have an idea on what is possible • ~FEI4 AFE equivalent Pixel size=50X100 (?)

  5. FIE4 pixel region Vs Pix65nm region (assuming y=50u) FEI4 2X2 REGION (100X500) “FEI5” 2X2 REGION (100X200) If area to be kept the same as FEI4, about 4X more logic can be added => Substantial area reduction => Ultimately the width of a pixel will limited by practical considerations (power distribution) and not the number of transistors! => Room to add functionality

  6. Snapshot of submitted pixel array Config. Logic Config. Logic Analog FE Future Digital Region nXm pixels Analog FE Bump opening • 25 mm y cell pitch but 50mm bump y picth. • Power distribution will be major factor in the ultimate minimum dimensions • Bump mask not part of the submitted layout (same size as FEI4)

  7. ATPIX65A FEND BLOC DIAGRAM Passive RC: gate leakage limited TDAC (+/- 4b tuning) Preamp. 17fF Feedback cap. Variable “Rff” Inject Bloc Single to differential+ Comparator “preamp” Comparator • Uses only native 65nm Transistors • 2mA to 25mA @ 1.2V

  8. ATPIX65A: Atlas Pixel prototype array 16 X 32 array 25m X 125m pixels Pixels with Added mimcaps (31,27,22,18) Pixels with Added sensors (row 11:31)

  9. Test results: front end waveforms Chan 15/32 Qin: 2ke Preamp out Single to Diff. out Chip found to work as expected! VDD=1.2V I= 5mA per pixel (can be as low as 2mA)

  10. Test results: front end waveforms Chan 15/32 Qin: 2ke to 10ke- Qin=10ke-; 5IFF settings

  11. Timewalk @Preamp current of 2mA and 0.2mA

  12. ATPIX65A: ENC for some columns Channels with Diodes (3 types) . . . . Channels with mimcaps

  13. ATPIX65: ENC Vs Preamp Bias

  14. ATPIX65A: Noise and Threshold distribution s > than FEI4 (as expected!) Channels with caps or diodes

  15. ATPIX65A: Threshold tuning Sigma untuned ~350e- rms Sigma Tuned < 60e- rms ---- 565e- p-p tuned ----

  16. Radiation effects on DC bias voltages • VG of diode connected transistors at fixed current (in mV) • Different size transistors • Small/negligible change in threshold voltages of PMOSs/NMOSs • PMOS threshold variation more pronounced! • Some measurement errors in the low current regime (meter impedance and esd diodes leakage)

  17. Radiation effects: Threshold and noise Green: chipB > 600Mrad Blue: chipAunirradiated ChipB: ENC=110e- ChipA: ENC=94e- Different chips. Under same bias conditions except for Vth Modest ENC increase (but only 2 chips) Preliminary results!

  18. Conclusions Chip works as expected Good results SEU evaluation under way (See talk by MohsineMenouni CPPM) Promising process. It offers: Very high integration density Inherent very high radiation tolerance A reasonable number of devices types for extra design flexibility Availability of high quality passives A high number of metal levels

  19. Backup slides

  20. Fe55 spectrum as detected by one of the integrated sensors 2154 KeV (2.9KeV? May be partial 5.9KeV charge collection?) For the experiment to agree with theory (for the 5.9KeV), injection cap has to be corrected by 15% . Still being reviewed! Noise artificially Limited 5154 KeV (theory; 5.9KeV?) 1040e- pulser injection ~3.7keV. Assuming Cinj to be nominal. Chip2 high gain mode. Sensor@-8V

  21. 65nm: Some transistor test result • No noise degradation at lower nodes • No thermal noise increase with radiation • No or little 1/f noise increase with radiation Same gate capacitance M. Manghisoni et al. TWEPP 2011

  22. 65nm: Some radiation tolerance results Threshold voltage Leakage current S. Bonacini et al. TWEPP 2011 65 nm devices seem to outperform their 130nm counterparts in their tolerance to ionizing radiation !

  23. ATPIX65: ENC Vs Diode bias

  24. ATPIX65: Threshold Vs Preamp current

  25. ATPIX65: Threshold Vs feedback current

  26. Lower part of the Am241 spectrum as detected by one of the integrated sensors ? http://spie.org/x20060.xml?ArticleID=x20060 ? (V) Chip1 low gain mode Very preliminary! Work in progress! Low statistics

  27. ATPIX65: ENC Vs IFF (feedback current)

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