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Reconfigurable Computing in the Undergraduate Curriculum

Reconfigurable Computing in the Undergraduate Curriculum. Jason D. Bakos Dept. of Computer Science and Engineering University of South Carolina. Our Courses. CSCE 611: Advanced Digital Design My course Behavioral design with VHDL CSCE 313: Embedded Systems Design Gang Quan’s course

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Reconfigurable Computing in the Undergraduate Curriculum

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  1. Reconfigurable Computing in the Undergraduate Curriculum Jason D. Bakos Dept. of Computer Science and Engineering University of South Carolina

  2. Our Courses • CSCE 611: Advanced Digital Design • My course • Behavioral design with VHDL • CSCE 313: Embedded Systems Design • Gang Quan’s course • Use EDK and XUP boards to design embedded systems • CSCE 491: Capstone System Design • Rotating instructors • Use XUP boards to design something • Last Fall I used System Generator for DSP to design active noise cancelation system

  3. Course Goals • CSCE 611: Advanced Digital Design • Teach students: • design methodology • design automation • design flow • design hierarchy • simulation, verification, test benching • computer architecture • design and verify an actual computer system • explore design trade-offs through implementation • Industry-standard CAD tools • Mentor FPGA Advantage, Xilinx ISE • FPGA design

  4. Course Goals • More specifically: • Manage design complexity of large-scale digital systems • VHDL • Graphical design for VHDL generation • Microarchitecture design • MIPS instruction set architecture / assembly language programming • MIPS CPU architecture • Memory hierarchy, cache • Bus functional models / memory interface design • Exceptions and interrupts

  5. Course Outline • Class times divided between lectures and supervised lab • Tutorials used to teach the tools and design flow • Yields the ALU design • Projects: • ALU testbench design • Multi-cycle CPU design • tested against testbench provided by instructor • Memory interface and bus design • tested against memory model containing significant comprehensive test program • Test processor on FPGA • Pipelined CPU, I/D cache, testbenches, synthesis and test • Originally used Annapolis FPGA PCI card with off-chip DRAM • Currently working on new design flow: • integrate student processor into EDK • target XUP system • develop software framework (drivers, MIPS cross-gcc, etc.) • debug with ChipScope

  6. Future Course • Extend processor design: • FP units • out-of-order execution • CMP and Level-2 cache • Run parallelized code and performance testing

  7. FPGA Advantage

  8. FPGA Advantage

  9. FPGA Advantage

  10. FPGA Advantage

  11. FPGA Advantage

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