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Introduction to FPGA and DSPs

Introduction to FPGA and DSPs. Joe College, Chris Doyle, Ann Marie Rynning. Field Programmable Gate Arrays. Architecture. Logic Block Interconnection Input/Output Switch Box Connect Block. Architecture. Logic Block Options Transistor pairs

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Introduction to FPGA and DSPs

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  1. Introduction to FPGA and DSPs Joe College, Chris Doyle, Ann Marie Rynning

  2. Field Programmable Gate Arrays

  3. Architecture Logic Block Interconnection Input/Output Switch Box Connect Block

  4. Architecture • Logic Block Options • Transistor pairs • Basic small gates (such as two-input NAND’s or exclusive-OR’ s) • Multiplexers • Look-up tables (LUT’s) • Wide-fanin AND-OR structures • Granularity Logic Block Interconnection Input/Output Switch Box Connect Block

  5. Architecture Logic Block Interconnection Input/Output Switch Box Connect Block Altera’s Stratix II ALM

  6. Architecture Logic Block Interconnection Input/Output Switch Box Connect Block Xilink’s Virtex 4

  7. Architecture • Routing Options • From nearest neighbor mesh to much more complex, like that in multiplexers • Wire segments of varying lengths • Delay Considerations • Density Considerations Logic Block Interconnection Input/Output Switch Box Connect Block

  8. Architecture Logic Block Interconnection Input/Output Switch Box Connect Block • Provide programmable multiplexers signals • Connect shorter local wires to longer-distance routing resources

  9. Architecture Logic Block Interconnection Input/Output Switch Box Connect Block • Used to change the direction of a signal

  10. Programmable Switch Technology • SRAM • Antifuse • EPROM Control Pass Gate SRAM SRAM Cell Cell 0 1 Multiplexer 0 or 1 MUX

  11. Programmable Switch Technology • SRAM • Antifuse • EPROM Disadvantages Volatile External Permanent Memory Required Large Area Required Advantages Reprogrammable, easily and quickly Requires only standard integrated circuit process technology (as opposed to Antifuse)

  12. Programmable Switch Technology • SRAM • Antifuse • EPROM 0 1

  13. Programmable Switch Technology • SRAM • Antifuse • EPROM Disadvantages Not reprogrammable; links made are permanent Requires extra circuitry to deliver the high programming voltage Advantages Small size Relatively low series resistance Low parasitic capacitance

  14. Programmable Switch Technology • SRAM • Antifuse • EPROM Word Line Control Gate - - Oxide Layer Bit Line Floating Gate 1 Drain Source Word Line Control Gate - - - - - - - Oxide Layer Bit Line 0 Floating Gate Drain Source

  15. Programmable Switch Technology • SRAM • Antifuse • EPROM Disadvantages High resistance of EPROM transistors High static power consumption UV light exposure needed to reprogram Advantages No external memory required; retains memory even without power Reprogrammable

  16. FPGA Producers Major Producers Smaller Producers (specialty)

  17. Digital Signal Processors

  18. Intel AMI Bell Labs NEC and AT&T TI, Motorola, Analog 1978 1979 1980 Today Brief History of DSPs

  19. Analog Blackfin • DSP • RISC MCU • Dual core • Clock control

  20. Analog Blackfin • Fast MAC • Parallelism • Pipelines • Close/fast storage • Multiple memories • High-bandwidth buses • External interface

  21. Analog Blackfin • Fast MAC • Parallelism • Pipelines • Close/fast storage • Multiple memories • High-bandwidth buses • External interface

  22. Analog Blackfin • Fast MAC • Parallelism • Pipelines • Close/fast storage • Multiple memories • High-bandwidth buses • External interface

  23. Analog Blackfin • Fast MAC • Parallelism • Pipelines • Close/fast storage • Multiple memories • High-bandwidth buses • External interface

  24. Analog Blackfin • Fast MAC • Parallelism • Pipelines • Close/fast storage • Multiple memories • High-bandwidth buses • External interface

  25. Analog Blackfin • Fast MAC • Parallelism • Pipelines • Close/fast storage • Multiple memories • High-bandwidth buses • External interface

  26. Analog Blackfin • Fast MAC • Parallelism • Pipelines • Close/fast storage • Multiple memories • High-bandwidth buses • External interface

  27. Analog Blackfin • Fast MAC • Parallelism • Pipelines • Close/fast storage • Multiple memories • High-bandwidth buses • External interface

  28. Analog Blackfin • DSP • RISC MCU • Dual core • Clock control

  29. Analog Blackfin • DSP • RISC MCU • Dual core • Clock control

  30. Analog Blackfin

  31. Analog Blackfin • DSP • RISC MCU • Dual core • Clock control

  32. Analog Blackfin

  33. ASIC vs. µP vs. Reconfigurable • Application Specific Integrated Circuit • Designed to perform a specific computation • Circuit cannot be altered after fabrication • Software Programmed Microprocessors • Modification with software • Slower than ASICs • Reconfigurable Computing • FPGAs and DSPs • Easily modifiable • Larger Area

  34. Virtex-4 FPGA Xilinx 500 MHz Processor 18-Bit MACS 48-Bit Accumulator Up to 1392K Bytes of On-Chip Memory Brand-New Blackfin DSP Analog Devices 600 MHz Processor Two 16-Bit MACS 40-Bit Accumulator 308K Bytes of On-Chip Memory Somewhat Older Comparison

  35. Comparison Criteria • Performance – MIPS, MMACS, MHz • Price • Development Tools • Supply Voltage • Implementation Time • Flexibility • Most Importantly: Comfort Level

  36. FPGA: Virtex-4 DSP Slice

  37. FPGA: Virtex-4 DSP Slice

  38. DSP: Blackfin Processor Core

  39. DSP: Blackfin Processor Core

  40. DSP: Blackfin Processor Core

  41. How to Use and Program an FPGA • Write HDL code • Generate Netlist • Place and Route • Generate Binary File • Power On FPGA • Configure FPGA • Verilog • VHDL (Very High Speed Integrated Circuit Hardware Description Language)

  42. How to Use and Program an FPGA • Write HDL code • Generate Netlist • Place and Route • Generate Binary File • Power On FPGA • Configure FPGA • Lists components that are connected to each other • Lists connections between components, power, and ground

  43. How to Use and Program an FPGA • Write HDL code • Generate Netlist • Place and Route • Generate Binary File • Power On FPGA • Configure FPGA • Often performed by the FPGA company's proprietary software • Determines which logic blocks to use for each part of the program, to optimize • User validates

  44. How to Use and Program an FPGA • Write HDL code • Generate Netlist • Place and Route • Generate Binary File • Power On FPGA • Configure FPGA • Often performed by the FPGA company's proprietary software

  45. How to Use and Program an FPGA • Write HDL code • Generate Netlist • Place and Route • Generate Binary File • Power On FPGA • Configure FPGA • FPGA is initially in configuration mode

  46. How to Use and Program an FPGA • Write HDL code • Generate Netlist • Place and Route • Generate Binary File • Power On FPGA • Configure FPGA • Cable from your PC to the FPGA • Use a microcontroller on your board • Use a "boot-PROM" on your board, connected to the FPGA

  47. Using DSPs • C/C++/Assembly • Lots of development environments • Documentation • Interfacing • Common operations • Porting

  48. Using DSPs • C++/Assembly • Lots of development environments • Documentation • Interfacing • Common operations • Porting

  49. Using DSPs • C++/Assembly • Lots of development environments • Documentation • Interfacing • Common operations • Porting

  50. Comparison Chart

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