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FPGA Editor Lab Introduction. Objectives. After completing this lab, you will be able to: Analyze the contents of a slice Add a probe Change I/O locations and contents View a constrained path and take steps to improve the performance of a net. Rhett Whatcott:
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Objectives After completing this lab, you will be able to: • Analyze the contents of a slice • Add a probe • Change I/O locations and contents • View a constrained path and take steps to improve the performance of a net
Rhett Whatcott: v6.1: Added note on design description. Lab Design: Correlate and Accumulate
Rhett Whatcott: v5.2: Changed slide. General Flow • Step 1: Implement the Design and Launch FPGA Editor • Step 2: Analyze Slice Contents • Step 3: Add a Probe • Step 4: Modify IOB Properties • Step 5: Move an IOB’s Location • Step 6: Analyze Timing Results • Step 7: View a Path • Step 8: Reroute a Net