Introduction to FPGA Tools

1. Introduction to FPGA Tools ECE 645 – Computer Arithmetic

2. Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Specification (Lab Experiments) VHDL description (Your Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31downto0); data_output: out std_logic_vector(31downto0); out_full: in std_logic; key_input: in std_logic_vector(31downto0); key_read: out std_logic; ); end AES_core; Functional simulation Synthesis Post-synthesis simulation ECE 645 – Computer Arithmetic

3. Design process (2) Implementation Timing simulation Configuration On chip testing ECE 645 – Computer Arithmetic

4. Design Process control from Active-HDL ECE 645 – Computer Arithmetic

5. Simulation Tools Many others… ECE 645 – Computer Arithmetic

6. ECE 645 – Computer Arithmetic

7. ECE 645 – Computer Arithmetic

8. Synthesis Tools … and others ECE 645 – Computer Arithmetic

9. Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; ECE 645 – Computer Arithmetic

10. Features of synthesis tools • Interpret RTL code • Produce synthesized circuit netlist in a standard EDIF format • Give preliminary performance estimates • Some can display circuit schematics corresponding to EDIF netlist ECE 645 – Computer Arithmetic

11. Implementation • After synthesis the entire implementation process is performed by FPGA vendor tools ECE 645 – Computer Arithmetic

12. ECE 645 – Computer Arithmetic

13. Translation Synthesis Circuit netlist Timing Constraints Constraint Editor Native Constraint File Electronic Design Interchange Format EDIF NCF UCF User Constraint File Translation Native Generic Database file NGD ECE 645 – Computer Arithmetic

14. Sample UCF File • # • # Constraints generated by Synplify Pro 7.3.3, Build 039R • # • # Period Constraints • #Begin clock constraints • #End clock constraints • # Output Constraints • # Input Constraints • # Location Constraints • # End of generated constraints • NET "clock" LOC = "P88"; • NET "control(0)" LOC = "P50"; • NET "control(1)" LOC = "P48"; • NET "control(2)" LOC = "P42"; • NET "reset" LOC = "P93"; • NET "segments(0)" LOC = "P67"; • NET "segments(1)" LOC = "P39"; • NET "segments(2)" LOC = "P62"; • NET "segments(3)" LOC = "P60"; • NET "segments(4)" LOC = "P46"; • NET "segments(5)" LOC = "P57"; • NET "segments(6)" LOC = "P49"; ECE 645 – Computer Arithmetic

15. Pin Assignment P93 P88 SEGMENTS(0) SEGMENTS(1) CLOCK P39 SEGMENTS(2) CONTROL(0) SEGMENTS(3) CONTROL(1) LAB2 P67 SEGMENTS(4) CONTROL(2) SEGMENTS(5) RESET P42 SEGMENTS(6) P62 P46 P60 P48 P49 P50 P57 FPGA ECE 645 – Computer Arithmetic

16. XSA Board Connectivity ECE 645 – Computer Arithmetic

17. Constraints Editor ECE 645 – Computer Arithmetic

18. Circuit netlist ECE 645 – Computer Arithmetic

19. Mapping LUT0 LUT4 LUT1 FF1 LUT5 LUT2 FF2 LUT3 ECE 645 – Computer Arithmetic

20. Placing FPGA CLB SLICES ECE 645 – Computer Arithmetic

21. Routing FPGA Programmable Connections ECE 645 – Computer Arithmetic

22. Static Timing Analyzer • Performs static analysis of the circuit performance • Reports critical paths with all sources of delays • Determines maximum clock frequency ECE 645 – Computer Arithmetic

23. Static Timing Analysis tP logic out in clk D D Q Q tCritical = tP FF + tPlogic + tS FF • Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers ECE 645 – Computer Arithmetic

24. Static Timing Analysis • Min. Clock Period = Length of The Critical Path • Max. Clock Frequency = 1 / Min. Clock Period ECE 645 – Computer Arithmetic

25. Configuration • Once a design is implemented, you must create a file that the FPGA can understand • This file is called a bit stream: a BIT file (.bit extension) • The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information ECE 645 – Computer Arithmetic

26. Resources & Required Reading Spartan FPGA devices • Xilinx Spartan-3 FPGA Family: • Complete Data Sheets • Module 1: Introduction & Ordering Information • Module 2: Functional Description • Xilinx Virtex-II 1.5V FPGA Family: • Complete Data Sheets • Module 1: Introduction & Ordering Information • Module 2: Functional Description ECE 645 – Computer Arithmetic

27. Resources & Required Reading FPGA Tools Integrated Interfaces: Active-HDL with Synplify® http://www.aldec.com/Previews/active_synplify.htm Integrated Synthesis and Implementation http://www.aldec.com/Previews/synthesis_implementation.htm ECE 645 – Computer Arithmetic

28. Hands-on Session Enough Talking Let’s Get To It!!Brace Yourselves!! ECE 645 – Computer Arithmetic

29. Y [3:0] 1 1 neg_Y ar_log ALU Schematic arith [1:0] A[3:0] B[3:0] A + B 0 1 A - B 2 A <<< 1 A >>> 1 3 0 0 logic [1:0] A and B 0 1 A or B 2 A xor B A xnor B 3 ECE 645 – Computer Arithmetic

30. Questions? ECE 645 – Computer Arithmetic