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Levan Babukhadia

This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentation In Slide Show, click on the right mouse button Select “Meeting Minder” Select the “Action Items” tab

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Levan Babukhadia

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  1. This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentation • In Slide Show, click on the right mouse button • Select “Meeting Minder” • Select the “Action Items” tab • Type in action items as they come up • Click OK to dismiss this box This will automatically create an Action Item slide at the end of your presentation with your points entered. FPGA’s for DFEF Levan Babukhadia SUNY at Stony Brook http://www-d0.fnal.gov/~blevan

  2. One DFE Mother Board receives trigger data for two FPS -wedges phi wedge 1 phi wedge 2 L1 L2 What we know : Find/Use Clusters in V-orient Find/Use Clusters in U-orient Find Clusters in V-orient (L1V) Find Clusters in U-orient (L1U) L1U OR L1V firmware fits in XCV400 @ 75%. L1U AND L1V firmware fits in XCV600 @ 95%. Report 8 L1 Counts L1U: HEl, HPh, LEl, LPh; L1V: HEl, HPh, LEl, LPh; to FPSS via LVDS Report clusters (max of 12U and 12V) to FPSS via LVDS

  3. Nomenclature • Most elementary components of the DFEF Level 1 and Level 2 (L1/2) algorithms are: • 1,2L1U The L1 cluster finder in a given -wedge (specified as 1 or 2, in the subscript of ) and in one (U) orientation. So, in principle, 1,2L1U only needs to determine the four distinct types [which are: “High Electron” (HEl), “High Photon” (HPh), “Low Electron” (LEl), and “Low Photon” (LPh)] of the L1 cluster counts in this orientation. • 1,2L1V The same as 1,2L1U, except for the other (V) orientation. • 1,2L2UV The L2 algorithm for potentially re-finding the clusters (unless the clusters identified by 1,2L1U and 1,2L1V could be used) and for determining priority for their reporting. To determine such priorities intelligently, BOTH U and V cluster information must be available and used at the same time, hence the L2 algorithm has to have U and V combined. In other words, there is not much sense in having 1,2L2U and 1,2L2V separately, except for the simplified, but quite possibly most realistic implementation, of the L2 algorithm, in which the first 12 found clusters, starting from the lowest , are to be reported in each orientation; Thus, in this case, U and V would be decoupled. • Note that 1,2 is used for the above components of the algorithms as these components are identical for the two 1,2-wedges.

  4. Nomenclature • So, at the most fundamental level, the four components of the DFEF L1/2 algorithm on a single DFE MB can be identified as follows: (1) 1L1 1L1U 1L1V ; (2) 1L2 1L2UV ; (3) 2L1  2L1U 2L1V ; (4) 2L2 2L2UV ; (i.e. there seems to be no rationale in considering L1U and L1V separately, given that they each would need at least one 400 FPGA.) • And two more useful abbreviations: • DWDB - Double Wide Daughter Board. • SWDB - Single Wide Daughter Board.

  5. “Obvious” Constraints for DWDB usage in DFEF • There can only be up to 3 FPGA’s on one DWDB, so two of the four components of the DFEF algorithm must be combined in one FPGA. • Transferring of the 1,2L1 clusters (i.e. not counts) from one FPGA to another is practically impossible (would take too much time). • Without loss of generality, there appear to be only 4 independent combinations of interest as follows (also indicated is the corresponding estimated usage of FPGA’s): (1) 1L1+2L1, 1L2, and 2L2  at least >1000, 600, and 600. (2) 1L1+2L1 and 1L2+2L2  at least >1000 and >~1000. (3) 1L1, 2L1, and 1L2+2L2  at least 800, 800, and >~800. (4) 1L1+1L2 and 2L1+2L2  at least 1000 and 1000. • All of these combinations are feasible to implement from the point of view of the availability of the I/O buses on the DWDB/MB. • However, there is obvious advantage for the combination (4), both cost-wise and from the point of view of most natural logical break up of the DFEF algorithm between two -wedges.

  6. XCV1000 1L1+ 1L2 XCV1000 2L1+ 2L2 Not used Double-wide DB with BG560 footprints Proposed Configuration for DFEF with DWDB MB Price Tag: $2,050 ( $1,025 x 2 + $2,050 ) COMMENTS: (1) This is less expensive than the smallest imaginable configuration (see the following slides). (2) Allows switching to Virtex-E FPGA’s where for the same price one can get significantly higher speed grade (-6 instead of -4). (3) If this configuration is chosen, would also advocate having one MB/DWDB with ALL 3 FPGA slots filled with 1K FPGA’s -- should be useful in commissioning!

  7. XCV600 1L1 XCV600 2L1 XCV800 1L2+2L2 Double-wide DB with BG560 footprints Smallest Imaginable Configuration for DFEF with DWDB MB Price Tag: $2,275 ( $650 x 2 + $975 ) COMMENTS: (1) L1 algorithms will be rather tight in the 600’s (~95%). (2) May need more than 800 for the L2 for two -wedges, especially if the cluster finding has to be repeated (cannot transfer clusters from the other two FPGA’s in reasonable time).

  8. XCV600 L2CFT XCV600 L2CPS XCV400 L1 CFT/CPS Double-wide DB with BG560 footprints Comparison: Default Configuration for CTOC (DWDB) MB Price Tag: $1,700 ( $650 x 2 + $400 )

  9. “Obvious” Constraints for SWDB usage for DFEF • Must have two SWDB’s so as to be able to access all 10 input links and each SWDB must process one -wedge. • There can be up to 5 FPGA’s on a SWDB, but a backend (fifth) chip must be present to access output links. • On each SWDB, one now has to worry about L1 and L2 for that . Then the only two possibilities are: (1) L1+L2  at least >1000. (2) L1 and L2  at least >600, and >~600. • (1) is no different than the proposal with DWDB with two 1000 FPGA’s, except: (a) would use two SWDB’s for no real good reason, (b) 1000 FPGA can not go in the backend (maximum being 800) and if it goes elsewhere, then at least one 300 should be put in the backend, or else jumper cables should put across (if possible). • (2) is more expensive (two -wedges would need 4x$650 > 2x$1025) than the proposal with DWDB (2 1K FPGA’s) and uses 2 DBs. • Any further break-up of algorithms (say L1  L1U and L1V) would only increase the cost (as well as create other problems).

  10. XCV600 1L1 XCV600 2L1 Not used Not used XCV600 1L2 XCV600 2L2 Not used Not used Not used Not used Single-wide DB with BG432 footprints Single-wide DB with BG432 footprints Smallest Imaginable Configuration for DFEF with SWDB MB Price Tag: $2,000 ( $500 x 4 ) COMMENTS: (1) L1 algorithms will be rather tight in the 600’s (~95%). (2) May need more than 800 for the L2 reporting. (3) Cost is more than with DWDB and two 1000’s. (4) For this footprint, there are only small size (300, 400, and 600) FPGA’s available in Virtex-E family.

  11. XCV600 Tracks Pt1 XCV600 Tracks Pt1 XCV400 Tracks Pt2 XCV400 Tracks Pt2 XCV300 Trk/Cluster matching XCV300 Trk/Cluster matching XCV400 Tracks Pt3 XCV400 Tracks Pt3 XCV400 Tracks Pt4 XCV400 Tracks Pt4 Single-wide DB with BG432 footprints Single-wide DB with BG432 footprints Default Configuration for DFEA MB Price Tag: $4,000 ( $500 x 2 + $400 x 6 + $300 x 2 )

  12. MB 400 400 400 400 400 400 400 400 Single-wide DB with BG432 footprints Double-wide DB with BG560 footprints

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