A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment

1. A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group Department of Physics, Southern Methodist University Dallas, Texas 75275, USA liu@physics.smu.edu

2. Outline • Introduction • Design of the serializer • Test of the serializer • Lab test • Radiation test • Cryogenic test • Future work • Conclusion 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

3. Introduction – Possible application 1 • Optical data links of the ATLAS liquid argon calorimeter • 1524 optical links in total • One optical link per front-end-board (FEB) • 1.6 Gbps each link • Radiation tolerance on the transmitter side • ATLAS liquid argon calorimeter upgrade • 10x luminosity • Removal of analog Level-1 trigger sum from FEBs and transfer continuously digitized data off the detector • Requirements on serializers • 100 Gbps per FEB • 100 mW/Gbps for the serializer • Redundancy to improve the link reliability • 10x radiation tolerance The ATLAS detector and liquid argon calorimeter 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

4. Introduction – Possible application 2 E • Advantage of liquid argon time projection chambers (LArTPCs): • Full 3D event reconstruction, sub-mm position resolution • dE/dx for particle ID, e/γ separation >90% • Low threshold of particle energies →1 - 2 MeV • Advantages of cold front-end electronics • Low noise (low input capacitance)  noise independent on the fiducial volume • Multiplexing to minimize the number of cables and feedthroughs  low cost, low outgassing, low leakags, low thermal load • Requirements on cold front-end electronics • Cryogenic operation (89 K) • High reliability 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

5. Introduction – Technology used • The serializer is designed and fabricated in a commercial 0.25 m Silicon-on-Sapphire (SOS) CMOS technology • The major features of the technology are • Advantages of the SOS CMOS technology include • Low parasitic capacitance  Fast • Low crosstalk between circuit elements  Low noise • Radiation tolerance at transistor level  greatly simplifies our design 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

6. Design of the serializer LCPLL 3 mm serializer 3 mm Die micrograph Design diagram • A ring oscillator based PLL provides clocks up to 2.5 GHz • A 16:1 CMOS multiplexer has a binary tree architecture • A differential CML driver drives serial data at 5 Gbps to coax cables • The ASIC was submitted for fabrication in Aug 2009 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

7. Test setup LOCS1 #1 • An FPGA board provides a 312.5 MHz clock and 16 bit parallel data to a chip carrier board, both in LVDS • 5 Gbps PRBS serial data are monitored using an oscilloscope or BERT 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

8. Lab test Eye diagram at 5 Gbps The mask is adapted from FC 4.25 Gbps and scaled to 5 Gbps 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

9. Radiation test Ref chip and FPGA shielded • Setup: • 200 MeV proton beam at IUCF • 2 chips in the beam and 1 chip shielded (ref) • Results: • Total ionization dose effects • All chips continue to function throughout the test • The power supply currents (IDD) change less than 6% during the irradiation. • Single event effects • Single bit errors: 5 bit flips in total  BER < 10-17 in sLHC • Synchronization errors: 28 in total  3 errors in 10 year operation time of sLHC Chips in the beam Beam outlet Beam Stop Chips in the beam Ref chip shielded 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

10. Cryogenic test 300 K, 5.2 Gbps, VDD 2.5 V • At 77 K the serializer has a wider open eye diagram with faster rise/fall times, smaller jitter and larger amplitude than those at room temperature. • The chip functions well with VDD = 1.8 V.  One of the design guides to guarantee the 15-year life time at cryogenic temperature. The reliability of the serializer at cryogenic temperature will be studied. 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee 300 K, 5 Gbps, VDD 1.8 V 77 K, 5.2 Gbps, VDD 2.5 V

11. Future work Parallel optical links may be a solution for 100 Gbps data rate/FEB • Two serializer chips with a 12-way fiber ribbon per FEB. • Each chip has an array of six 16:1 serializers each running at 10 Gbps. • One of the six serializers can be configured as a redundant channel. • The clock unit may be shared by the serializers to reduce the power consumption. 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee

12. Conclusion • A 5 Gbps 16:1 serializer ASIC in a commercial 0.25 μm SOS CMOS technology has been developed. • Laboratory test indicates that we have achieved the design goals. • Irradiation test indicates that the ASIC meets the application requirements. • Cryogenic test indicates that the ASIC may be used in cryogenic temperature • A 6-lane serializer array with 10 Gbps/lane with redundancy capability is under development. 2010 NSS-MIC – 2 NOV 2010 – Knoxville, Tennessee