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Lab 2 Basic Gates in a PLD

Lab 2 Basic Gates in a PLD. Module M2.3 Section 4.2 Experiment 2 (p. 63). Experiment 2. CUPL Header. CUPL Comments. CUPL Inputs and Outputs. CUPL Logic Equations. CUPL Chip Diagram in .DOC File. Fuse Plot for !X. Structure of the GAL 16V8 PLD. Fuse Plot for !Y.

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Lab 2 Basic Gates in a PLD

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  1. Lab 2Basic Gates in a PLD Module M2.3 Section 4.2 Experiment 2 (p. 63)

  2. Experiment 2

  3. CUPL Header

  4. CUPL Comments

  5. CUPL Inputs and Outputs

  6. CUPL Logic Equations

  7. CUPL Chip Diagramin .DOC File

  8. Fuse Plot for !X

  9. Structure of the GAL 16V8 PLD

  10. Fuse Plot for !Y

  11. Structure of the GAL 16V8 PLD

  12. Fuse Plot for X & Y

  13. Structure of the GAL 16V8 PLD

  14. Fuse Plot for !(X & Y)

  15. GAL 16V8 Polarity Control OE A C Pin B Polarity X X closed B = 0 C = A ­ open B = 1 C = !A

  16. Fuse Plot for X & Y

  17. Fuse Plot for !(X & Y)

  18. Fuse Plot for X # Y

  19. Structure of the GAL 16V8 PLD

  20. Fuse Plot for !(X # Y)

  21. Fuse Plot for X $ Y

  22. Structure of the GAL 16V8 PLD

  23. Fuse Plot for !(X $ Y)

  24. JEDEC File

  25. JEDEC File Header

  26. JEDEC File Fuse Map

  27. Experiment 2Basic Gates • Modify the file, Exp2.pld, by using pins 6 and 7 for the two inputs X and Y respectively. • Modify the simulation file, Exp2.si on the web to use your header. • Compile the program using WinCupl and run the simulation. • Print out the chip diagram from the .DOC file. • Print out the fuse maps. • Program the GAL 16V8 chip.

  28. Experiment 2Basic Gates • Connect pins 6 (X) and 7 (Y) to Out1 and Out0. • Connect pins 12-15 to In4-In1. Print the truth table. Label each output column with the appropriate gate. • Connect pins 16-19 to In4-In1. Print the truth table. Label each output column with the appropriate gate. • Explain the fuse maps.

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