Balancing Interconnect and Computation in a Reconfigurable Array

1. Balancing Interconnect and Computation in a Reconfigurable Array Why you don’t really want 100% LUT utilization Dr. André DeHon BRASS Project University of California at Berkeley

2. Question How much interconnect do I need for my computing/programmable array? Problem(?): too little interconnect won’t be able to use all the gates/LUTs Typical subgoal: how much interconnect to use (almost) all LUTs?

3. Wrong Subgoal • Observation: • interconnect is dominant area on FPGAs • more important to use interconnect efficiently than to use LUTs efficiently • Different question/subgoal: • What level of interconnect gives the least implementation area for applications?

4. LUT Utilization predict Area?

5. Outline • Question: how much interconnect? • Teaser: less than 100% LUT utilization • Model • Application characteristics • Compose • Conclusions

6. N/2 cutsize N/2 Model Interconnect Requirements and Richness • Recursively partition (bisect) design • Look at I/O from each partition (subtree)

7. Regularizing Growth • How do bisection bandwidths shrink (grow) at different levels of bisection hierarchy? • Basic assumption: Geometric • 1 • 1/ • 1/2

8. Rent’s Rule • Long standing empirical relationship • IO = CNP • 0P 1.0 • Embodies geometric assumption (C,P) • Two parameters • C base of growth • P capture growth (a= 2P) • Captures notion of locality

9. (2 1)* => a=2 (2 2 2 1)* =>a=2(3/4) (2 2 1)* => a=(2*2)(1/3) =2(2/3) Define Network with Parameters

10. “Cartoon” VLSI Area Model (Example artificially small for clarity)

11. 1024 LUT Area Comparison 0.25 P=0.5 0.37 P=0.67 1.00 P=0.75 Effects of P on Area

12. Application Requirements: Benchmark Wide (MCNC)

13. Benchmark Parameters Interconnect requirements vary across applications.

14. Network Fixed Schedule • Network will have a fixed wiring schedule • Applications have varying requirements • To assess impact of mismatch • map to network schedules • look at area required

15. Mapping Problem • When design interconnect exceeds network • have to repartition to meet fixed wire schedules of target network • depopulating LUTs as necessary • See paper/poster for one approach

16. Resources  Area Model => Area

17. Picking Network Design Point (8l wire pitch; 2500l2 switchpoints; linear population)

18. Summary • Interconnect area dominates logic block area • Interconnect requirements vary • among designs • within a single design • To minimize area • focus on using dominant resource (interconnect) • may underuse non-dominant resources (LUTs)