Pre-Layout Estimation of Individual Wire Lengths

Pre-Layout Estimation of Individual Wire Lengths Srinivas Bodapati (Univ. of Illinois) Farid N. Najm (Univ. of Toronto) f.najm@toronto.edu

Introduction • Interconnect represents an increasingly significant part of total circuit delay • Longer interconnect is more significant • Interconnect is accurately known only after place/route • This leads to timing closure problems • Logic design is now coupled with physical design • Interconnect must be considered during: • Floorplanning, synthesis, timing verification • We need to be able to predict the length of individual wires before layout, say during technology mapping • Traditional wire load models give only average load Bodapati & Najm

Wire Load Models not Enough (Source: Kapadia & Horowitz, DAC-99) Bodapati & Najm

Previous Work • Previous work in this area: • Pedram and Preas, ICCD-89 • Average wire length for given pin-count • Heineken and Maly, CICC-96 • Wire-length distribution • Hamada, Cheng, and Chau, TCAD 8/96 • Average wire length for given pin-count • Others … • Previous work has focused on aggregate metrics (average, distribution) • Given the spread in wire-length values, individual wire length estimation is required Bodapati & Najm

Alternative • Traditional wireload models are failing: • They only predict average net behavior • They only predict wire capacitance, not length or resistance • Resistive shielding is important in DSM • We are developing wire length predictors (for individual wires or nets) that work at the netlist level, pre-layout • A black-box model is built using linear regression on a number of variables: • Base-length, expressed a function of the pin-count of a net • Various congestion metrics, expressed as functions of a number of local and global primitive variables • Technique verified using Cadence’s Silicon Ensemble Bodapati & Najm

Proposed Model Structure • General features of the model: • Short wires (less than 70 um) are excluded, due to noise • Mid-range wires are estimated via a regression model, built by a one-time up-front characterization process • Long wires (more than 7 pins) are handled via bounding box method Bodapati & Najm

Basic Parameters - Local • Local parameters capture significant attributes of individual nets and of the net neighborhood • The number of pins on a net (denoted Pnet) is known to affect net length: • We use Pnet as a key local parameter • Other local parameters are defined based on the notion of a neighborhood (data from the characterization set, table 4.1) Bodapati & Najm

Neighborhood - First Level • The first level neighborhood (denoted Nh1(i) ) of a given net i is defined as: • The set of all other nets connected to cells to which this net is also connected • In this figure, Nh1(10) = { 6, 7, 9, 11, 8, 12, 13 } Bodapati & Najm

Neighborhood - Second Level • The second level neighborhood (denoted Nh2(i) ) of a given net i is defined as: • The union of all first level neighborhoods of nets that are in the first level neighborhood of this net • In this figure, Nh2(10) = { 1, 2, 5, 11, 9, 14, 3, 4, 12, 13, 8, 15, 16 } Bodapati & Najm

Neighborhood • The neighborhood of a net is defined as the union of its first and second level neighborhoods • The neighborhood of net 10 is shown: • With this, define other local parameters (k = 2, 3, 4, 5, 6) : • Nknet is number of nets in the neighborhood that have k pins Bodapati & Najm

Basic Parameters - Global • Global parameters capture significant global attributes of the design: • Number of cells in the design, Nc • For k = 2, 3, 4, 5, 6, number of k-pin nets in the design, Nkagg • This is also the number of gates with k-pin nets at their output • Average cell width in this design, Wavg • Other global parameters are specified as parameters to be used by the layout engine: • Aspect ratio, R • Row utilization factor, U • In our work, R = 1 and U = 85% were kept constant Bodapati & Najm

Intermediate Variables • Intermediate variables are defined based on the basic parameters, and include: • Base length, Lnbase • Congestion metrics, Pkcon, k = 2, 3, 4, 5, 6, and N2oth , N3oth • Base length is defined based on Pnet , as the average of: • The net length if all cells on the net are placed in vertical stack • The net length if all cells on the net are placed in horizontal row • Thus: where Hcellis the height of a cell (in our case 12.60 um) Bodapati & Najm

Base Length is Important (data from the characterization set, table 4.1, excluding short wires) Bodapati & Najm

Low Pin-Count Nets Placed First • An observed key feature of Silicon Ensemble is that low pin-count nets (2, 3 pins) are placed first • Since these represent a large fraction of the total, this approach leads to a smaller overall net length • Consequences of this: • 2 or 3 pin nets are placed very close together, because very little else has been placed by then, hence limited relative placements • low pin-count nets are spread out on the layout surface irrespective of their impact on higher pin-count nets • low pin-count nets become the main obstacles to routing higher pin-count nets - they cause congestion • This motivates our definition of congestion metrics Bodapati & Najm

Congestion Metrics • A high pin-count net would be long if: • It has a large number of low pin-count nets in its neighborhood • These low pin-count nets are spread out over a large layout area • Focusing on 2-pin nets in the neighborhood, we capture the above with the following 2-pin congestion metric: • The term on the right is a measure of the number of possible ways and locations of placing a 2-pin net • Likewise, we define P3con , P4con , P5con , and P6con Bodapati & Najm

Net Length v.s. P2con (data from the characterization set, table 4.1, excluding short wires) Bodapati & Najm

One more Congestion Metric • The above metrics capture congestion and spread due to low pin-count nets that belong to the neighborhood • Other low pin-count nets, that do not belong to the neighborhood, can also impact net length, if: • A large number of them are placed in the same general layout area that the net neighborhood will occupy • These nets can become obstacles … they are in the way • For 2-pin nets, we capture this with the following: • Likewise, we define N3oth as the last congestion metric Bodapati & Najm

Net Length v.s. N2oth (data from the characterization set, table 4.1, excluding short wires) Bodapati & Najm

The Polynomial Model • With all the above variables, we express net length as: where f(.) is a polynomial template (quadratic or cubic is enough) • The polynomial coefficients are computed by linear regression, based on a set of benchmark circuits • We call these the characterization circuits (see next slide) • The technique was then tested on a different set of circuits • We call these the test circuits (shown later on) • Before showing the results, we will discuss the special case treatment for very short and very long wires Bodapati & Najm

The Characterization Circuits (ISCAS and MCNC benchmark circuits) Bodapati & Najm

Special Case: Short Wires • Length of short wires (less than about 70 um) was found to be very sensitive to various insignificant parameters: • Cell names, net names, order in which cells are listed • The circuit is alu2o (368 gates, 380 nets) • All that was varied in this case was the cell names in the netlist Bodapati & Najm

Special Case: Short Wires • This is probably due to the heuristic nature of the tools • This does not represent a problem with the P&R tool • Total net length is typically used as an objective function • Multiple layout solutions can have similar total net length • For purposes of individual net length estimation, these variations represent “noise,” which can be a problem • The noise is there for longer wires as well, but is not as bad (as we’ll see later); luckily, we are less concerned about short wires • Consequences: • Estimation of short wires is practically impossible • Individual wire length estimation cannot be done beyond a certain accuracy level; this “noise floor” depends on the tool Bodapati & Najm

Special Case: Long Wires • For nets with more than 7 pins, special case treatment was found to be required • Since these nets are routed “last”, then: • Their placement options become restricted, and • Their large neighborhoods are spread out • To handle these nets, we use a method based on the commonly used concept of a bounding box • Box area is estimated from intermediate variables • Box height is computed assuming each cell in different row • Use either result from Caldwell et al. or half-perimeter as the estimate of net length Bodapati & Najm

Experimental Results • Implementation: • ISCAS, MCNC circuits were optimized and mapped using SIS • Place & route was done with Cadence’ Silicon Ensemble • Library: • 102 cells • 1.40 um (metal pitch) • 4 metal layers • cell height is 12.60 um • core site width is 1.40 um • Characterization was done using the characterization circuits (shown previously) • Testing was done with the test circuits (see next slide) Bodapati & Najm

The Test Circuits (ISCAS and MCNC benchmark circuits) Bodapati & Najm

alu2o alu2o noise s1238o s1238o noise Results and Noise Bodapati & Najm

apex6o apex6o noise frg2o noise frg2o Results and Noise Bodapati & Najm

Results and Noise x3o x3o noise random10 random10 noise Bodapati & Najm

Long Wires - Results (data from all the test circuits) Bodapati & Najm

Long Wires - Noise (data from all the test circuits) Bodapati & Najm

Total Average Error (long wires data is from all the test circuits) Bodapati & Najm

Summary & Conclusion • Problem: • Interconnect can no longer be ignored • Wire load models are no longer good enough • Need prediction of individual wire lengths before layout • Proposed solution: • Black box model of net length based on various metrics that are extracted from the netlist - regression on polynomial template • Short wires excluded - due to noise • Long wires handled as special case - bounding box approach • Unavoidable noise is due to heuristics in P&R tools • Individual net length estimation is possible, within the limits due to this noise Bodapati & Najm

Pre-Layout Estimation of Individual Wire Lengths