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Pre-Layout Simulation

Pre-Layout Simulation. 本部份原本應該要最早做的，但若我們先利用 Schematic editor 畫好電路圖，進而直接轉出 hspice file ，就可免除人工撰寫 hspice file 的麻煩。 本部份是為了要確定電路可達到規格要求。. pre-layout simulation. Hspice. Inv.net. Spice file format(1/2). Spice file format(2/2). Transient Analysis―.TRAN Analysis （暫態分析）. SPICE circuit simulation.

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Pre-Layout Simulation

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  1. Pre-Layout Simulation • 本部份原本應該要最早做的，但若我們先利用Schematic editor畫好電路圖，進而直接轉出hspice file，就可免除人工撰寫hspice file的麻煩。 • 本部份是為了要確定電路可達到規格要求。 pre-layout simulation Hspice

  2. Inv.net

  3. Spice file format(1/2)

  4. Spice file format(2/2)

  5. Transient Analysis―.TRAN Analysis（暫態分析）

  6. SPICE circuit simulation Mn1 15 17 20 20 NMOS W=5U L=0.5U <AD=…> Mp1 15 17 12 12 PMOS W=10U L=0.5U <AD=…> Rgnd 20 0 1K Cload 15 0 100F .MODEL NFET NMOS <parameters> (from technology files) .MODEL PFET PMOS <parameters> (from tech. files) Vin 17 0 PULSE(V1 V2 TD TR TF PW PER) .DC Vin 0 VDD VSTEP .TRAN TSTEP TSTOP

  7. 傳輸延遲 （Propagation Delay）和上升下降時間 TpHL：從Vi 變化的50 % 到達Vo 變化（Vo 由High 至Low ) 的50 %之間所經過的時間。 TpLH：從Vi 變化的50 % 到達Vo 變化（Vo 由Low 至High）的50 %之間所經過的時間。 Tp：一般而言，TpHL 不會等於TpLH，因此我們定義Tp 為平均延遲時間，亦即： Rise time 指上升時間，output 由10 % 至90 % VDD Fall time 指下降時間，output 由90 % 至10 % VDD

  8. tf tr tpHL tpLH Propagation Delay Vin Vout (V) x 10-10 t (sec)

  9. 測量delay

  10. 修改netlist 檔 移掉subckt與pin腳宣告，加上PULSE波形輸入與測量Delay指令

  11. Modify netlist file

  12. Execute & Result

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