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ECE 353 Introduction to Microprocessor Systems

ECE 353 Introduction to Microprocessor Systems. Michael J. Schulte. Week 7. Topics. Clock and reset generation. Bus timing. Bus signal demultiplexing. System buffering Determining suitability of logic family interconnections. System Diagram. 80C188EB Package. Clock and Reset.

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ECE 353 Introduction to Microprocessor Systems

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  1. ECE 353Introduction to Microprocessor Systems Michael J. Schulte Week 7

  2. Topics • Clock and reset generation. • Bus timing. • Bus signal demultiplexing. • System buffering • Determining suitability of logic family interconnections.

  3. System Diagram

  4. 80C188EB Package

  5. Clock and Reset • Clock Generation • Internal Oscillator • External Oscillator • Processor Clock • Reset • Cold-start vs. warm-start • RC reset circuit • Microprocessor Supervisors • MAX807

  6. Bus Cycles • Basic Read Cycle Sequence at Bus Level • Diagram • Basic Write Cycle Sequence at Bus Level • Diagram • States and Phases • Bus Cycle State Diagram • Types of Bus Cycles • S2:0 indicate the type of bus cycle in progress.

  7. Bus Cycles • 80C188EB Bus Cycle Timing • Read Cycle • Write Cycle • Exercise: What type(s) of bus cycles are run? What address and data during each? 001A BA 1000 mov dx, 1000h 001D C7 07 1234 mov [bx], 1234h 0021 8A 07 mov al, [bx] 0023 EE out dx, al 0024 ED in ax, dx

  8. Demultiplexing • Multiplexed Signal Timing • Bus signal phases • Demultiplexing Strategies • Remote Demultiplexing • Local Demultiplexing • Implementation • Devices • Connections • Timing • Read • Write

  9. Fully-Buffered System • Advantages and Disadvantages • Signal Buffering • Address bus • Data bus • Transceivers • Control signals • Control bus • Contention issues • Terminology • Local bus • Buffered bus • Partial buffering

  10. Logic Family Compatibility • Logic family characteristics • Definitions • Logic families • DC noise margins • Driver characteristics • Receiver characteristics • Compatibility • Voltage • Current • Exercises • Capacitive loading • TTL to CMOS

  11. Wrapping Up • Reading for next week • Textbook chapters 10.7-10.10, 11

  12. 80C188EB Clock Generator

  13. MAX807

  14. Basic Read Cycle

  15. Basic Write Cycle

  16. Bus Cycle State Diagram

  17. Bus Cycle Types

  18. Read Cycle

  19. Write Cycle

  20. States & Phases

  21. 001A BA 1000 mov dx, 1000h

  22. 001D C7 07 1234 mov [bx], 1234h

  23. 0021 8A 07 mov al, [bx]

  24. 0023 EE out dx, al

  25. 0024 ED in ax, dx

  26. Logic Compatibility Exercises • For the following logic families, determine compatibility, noise margins, and fan-out. • 74ALS driving 74AC • 74AC driving 74ALS Note: For 74AC, top line is with CMOS load, bottom line is with TTL load.

  27. TinyLogicTM and Little Logic

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