ECE 353 Introduction to Microprocessor Systems

1. ECE 353Introduction to Microprocessor Systems Michael Schulte Final Exam Review

2. Final Exam Info • Held on on Saturday, May 17th from 7:45am to 9:45am in 3418 EH • Exam is 2 hours • Single 3x5 card • Calculators may be permitted for numeric calculations – I’ll send out email • Cumulative exam covering Modules 1-6 + Serial I/O (week 13) • Emphasis will be on conceptual comprehension • Review all educational objectives, homeworks, quizzes, and lecture notes

3. Review • Why do PC UARTs include data FIFOs? • What are the differences between synchronous and asynchronous comm? • How does an asynchronous receiver know when to sample each bit? Synchronous?

4. Review • A UART typically uses a clock 8x-16x the baud rate. Why? • What is the purpose of the parity bit? How is it calculated? • How does software flow control work? • Compare and contrast hardware and software flow control.

5. Review • What sorts of things does the RS-232 standardize? • On an RS-232 link, what information needs to be known in advance at both ends?

6. Review • What is an address boundary? • In regards to decoding, why do we care about boundaries? • What is the difference between memory-mapped I/O and isolated I/O? • What are the main signal groups you would expect to find on a parallel system bus?

7. Review • Why does the assembler need IMPORT/EXPORT directives? What effect do they have? • What addressing mode does the instruction LDR R0, label imply? • How is the instruction LDR R0, label encoded? What limits are there on label? • Why can’t the ADR pseudo-instruction work across AREA boundaries?

8. Review Session • In a processor with vectored interrupts, a timer interrupt is typically cleared automatically. In the ADuC7026, we had to do it in software. Why is this? • If you were designing transmitter and receiver logic for a serial port, how different would it be for synchronous communication versus asynchronous communication? • Consider the transmitter. • Consider the receiver.

9. Review • Create a look-up table to convert the values 0-9 to a pointer to the respective ASCIIZ equivalent strings (i.e. 4 converts to the address of a string “four”) • Write a code fragment to access the LUT. • What are the limitations on the LUT size? • What are the limitations on the size of the LUT elements? • When is it advantageous to use an LUT?

10. Number-to-String LUT INCLUDE aduc7026.inc AREA FLASH, CODE, READONLY sZero DCB "zero", 0 sOne DCB "one", 0 sTwo DCB "two", 0 sThree DCB "three", 0 sFour DCB "four", 0 sFive DCB "five", 0 sSix DCB "six", 0 sSeven DCB "seven", 0 sEight DCB "eight", 0 sNine DCB "nine", 0 num2text DCD sZero, sOne, sTwo, sThree, sFour, sFive, sSix, sSeven, sEight, sNine __main main_loop MOV R0, #0 ;value to look-up ADR R1, num2text ;LUT base address LDR R0, [R1, R0, LSL #2] ;do look-up B main_loop END

11. Review • What is a jump table? How is it used? • What are the advantages of using a stack frame? • Can register passing schemes be reentrant? • Why do some compilers use a combination of register passing and stack frames? • What is the difference between unpacked and packed BCD?

12. Review • What safeguards are necessary to safely implement battery-backed NV-SRAM? • What is the primary function of a reset circuit? • Why do RAMs typically implement two-level decoding? • How are the memory device signals (address, data, /CS, /WE, /OE) managed when creating memory banks with greater depth and width than a single device?

13. Review • What signals does the ADuC7026 use to support 8-bit and 16-bit access to 512kB of external memory space? • Why does the ADuC7026 use a multiplexed AD bus? Why isn’t address bit A0 used in a 16-bit memory space? What is the logic used to generate /BHE and /BLE? • Can we connect a 4-bit device by itself to the ADuC7026 bus? Any hazards? How to mitigate?

14. Review • At how many different addresses will a single physical location exist if a device is partially decoded? • If 0x12345 is stored as a 32-bit word at address 0x1000, show how it is stored in a little-endian system. Is either endian better than the other? • How does a watchdog timer work? • What type of rotary encoder would be best for a car stereo volume control? • What is a level-sensitive IRQ line?

15. Review • An ISR services a communications receiver. The interrupt occurs when a single byte of data is available at address 0x70000000. The ISR will call a subroutine scan, that gets the incoming data and looks for for a specified string. If detected, it returns R0<>0, otherwise returns R0=0. • Write the scan subroutine. Do not worry about context save/restore. Use a terminating 0 on the string to set the comparison length. Assume characters only appear once in the string (use “ATZ” for this example).

16. Scan Subroutine – Part 1 AREA SRAM, DATA, READWRITE count DCB 0 AREA FLASH, CODE, READONLY ;context save/restore omitted target DCB “ATZ”, 0 scan LDR R3, =(0x70000000) ;get data address LDRB R0, [R3] ;load data LDR R3, =(count) ;get count address LDRB R1, [R3] ;load current count ADR R4, target ;get target string address LDRB R2, [R4, R1] ;load current target character CMP R0, R2 ;it is the correct data? BNE not_correct ADD R1, R1, #1 ;advance count LDRB R2, [R4, R1] ;get next character CMP R2, #0 ;check for terminator MOV R0, #0 ;return failure as default, count unchanged MOVEQ R0, #1 ;return success MOVEQ R1, #0 ;reset count on success STRB R1, [R3] ;update count B scan_exit

17. Scan Subroutine – Part 2 not_correct LDRB R2, [R4] ;get first character CMP R0, R2 ;did we find the first character? MOV R1, #0 ;reset count as default MOVEQ R1, #1 ;if so, update count MOV R0, R1 ;use count as return value STRB R1, [R3] ;update count scan_exit MOV PC, LR ;return ;

18. Review • Write a data area and 2 subroutines (get/put) to implement a circular queue of size N=2n. Why is it better to have N=2n? If this queue is being used by a serial transmitter ISR and the main program, what hazards could occur?

19. Circular Queue – Part 1 ;assume subroutine use R0 to hold data to/from queue AREA SRAM, DATA, READWRITE buffer SPACE N head DCB 0 ;index of next item in queue to remove tail DCB 0 ;index of next available space in queue AREA FLASH, CODE, READONLY ;context save/restore omitted get LDR R3, =(tail) ;load indexes LDRB R2, [R3] LDRB R3, =(head) LDRB R1, [R3] CMP R2, R1 ;empty? BEQ get_done LDR R4, =(buffer) LDRB R0, [R4, R1] ;get data ADD R1, R1,#1 ;calculate new head index AND R1, R1,#(N-1) STRB R1, [R3] ;update head index get_done MOV PC, LR ;return

20. Circular Queue – Part 2 ;assume subroutine use R0 to hold data to/from queue put LDRB R3, =(head) ;load indexes LDRB R1, [R3] LDR R3, =(tail) LDRB R4, [R3] ADD R5, R4,#1 ;calculate updated tail index AND R5, R5,#(N-1) CMP R5, R1 ;will it overflow? BEQ put_done ;is full – we ignore new data in this implementation LDR R2, =(buffer) STRB R0, [R2, R4] ;store data STRB R5, [R3] ;update tail index put_done MOV PC, LR ;return END

21. Review - Timing Problem #1 • Assume we have the system shown here. • What is the worst-case data setup time (tWDS) requirement that we can support while keeping the total write cycle time to 150ns or less? (Assume all other timing has been met.) • Assume the following - • ADuC7026 with 40MHz external clock (T = 25ns) • tDECODERmin = 5ns, tDECODERmax = 15ns • tLATCHmin = 3ns, tLATCHmax = 8ns • Draw only the waveforms of interest on the handout, and write the inequality. • write cycle - write parameters - write control

22. Review - Timing Problem #2 • Assume we have the system shown here. • The SRAM requires that the address be stable for at least 45ns after the /WE pin is negated. Assume that there is no delay between consecutive writes (i.e. /MSx remains asserted), and a one clock delay if a read follows the write. • Assume the following - • ADuC7026 with 40MHz external clock (T = 25ns) • tDECODERmin = 5ns, tDECODERmax = 15ns • tLATCHmin = 3ns, tLATCHmax = 8ns • Draw only the waveforms of interest on the handout, and write the inequality. • read cycle - read parameters - read control • write cycle - write parameters - write control • consecutive write cycles • Is the device compatible? If the device is not compatible, what are our options?

23. Review • That’s all, folks!

24. Basic Read Cycle

25. Basic Write Cycle

26. Read Cycle Parameters

27. Write Cycle Parameters

28. Read Cycle Controls

29. Write Cycle Controls

30. Microprocessor/Memory System

31. Consecutive Write Cycles

32. Synchronous Communications frame Back

33. Asynchronous Communications -RS232 Framing • What do you need to know in order to figure out what the data is? Back