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Cadence Tempus™ Timing Signoff Solution . SSV Summit November 2013. Industry needs for n ext g eneration signoff. Signoff closure up to 40% of the design flow Need faster runtimes Capacity for +100M cell designs with 100s of timing views Better accuracy to reduce pessimism, power, area.
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Cadence Tempus™ Timing Signoff Solution SSV Summit November 2013
Industry needs for next generation signoff • Signoff closure up to 40% of the design flow • Need faster runtimes • Capacity for +100M cell designs with 100s of timing views • Better accuracy to reduce pessimism, power, area
TheTempus™ Timing Signoff Solution PERFORMANCE • Massively parallelized computation • Scalable to 100s of CPUs • Optimized data structures CLOSURE • Up to 10X reduction in closure time • Placement and routing aware • Unlimited MMMC capacity ACCURACY • Up to 10X faster path-based analysis (PBA) • Advanced process modeling • TSMC-certified accuracy Tempus– It’s about TIME
Performance backgroundStacked performance enablement • Optimized multi-threading • Distributed processing • Incremental & hierarchical analysis • Concurrent multi-mode multi-corner analysis • Parallelized path based analysis MMMC Concurrency Incremental Analysis Distributed Processing Flat Single View (Multi-Threading) Technology
Performance metrics Parallelized processing • Combines multi-threading with distribution • Simple setup • User specifies desired resources • Parallelization transparent to user • Up to 50M cells analyzed in one hour • Low memory footprint MMMC Concurrency Incremental Analysis Distributed Processing Flat Single View (Multi-Threading)
Concurrent MMMC view analysis • Analyzes all modes and corners in one timing session • Runs on one compute server • More than 2X faster with same hardware • Less than 20% memory overhead per additional timing view • Reduces hardware resource requirement MMMC Concurrency Incremental Analysis Distributed Processing Flat Single View (Multi-Threading)
Path-based analysis (PBA)Reduced pessimism and runtime • Graph based analysis is fast but inherently pessimistic • Path based analysis is slow but reduces pessimism • Accurate transitions and derates • Tempus solves PBA reporting runtimes • Parallelized computation Pessimism reduction
Tempus timing closure Place and route • Full timing/optimization solution • Delay and SI • Distributed MMMC • Physically aware • Setup/hold/DRV/leakage optimization • Path or graph based Tempus Physically aware ECO 2-3 Iteration Physical view (LEF/ DEF) Physically- aware optimization Hold, DRV, setup, leakage Distributed MMMC delay calculationand STA Timing closed
Tempus resonates with users What we said… Community feedback (courtesy of DeepChip)…
Global Foundries tapeout success • Presented at ARM® TechCon 2013 • Cortex®-A12 testchip • 28nm SLP Technology • Close collaboration • ARM, Global Foundries, Cadence • Full Cadence flow • Final signoff with Tempus! • Key Tempus technologies • MMMC analysis • Physically aware optimization
In summary • Cadence is solving the design complexity challenge • Eliminating the signoff bottleneck • Enables power, performance and time-to-market goals • Tempus™ accelerates timing analysis and closure by weeks • As much as 10x faster • Handles 100’s of millions of cells • Optimizes timing across hundreds of views • Strong customer demand • Multiple evaluations and customers • Early tapeout success More to come!
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