1 / 25

Interconnect Synthesis

Interconnect Synthesis. Buffering Related Interconnect Synthesis. Consider Layer assignment Wire sizing Buffer polarity Driver sizing Generalized buffering Blockages Wire segmenting Higher order delay models Noise Bus design Buffer library Simultaneous routing and buffering

modesta-curtis
Download Presentation

Interconnect Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Interconnect Synthesis

  2. Buffering Related Interconnect Synthesis • Consider • Layer assignment • Wire sizing • Buffer polarity • Driver sizing • Generalized buffering • Blockages • Wire segmenting • Higher order delay models • Noise • Bus design • Buffer library • Simultaneous routing and buffering • Simultaneous gate sizing and buffering

  3. Layer assignment • With advancing technology, buffering considering layer assignment becomes increasingly important. • Wire in higher layer has smaller delay. Thus, a buffer can drive longer distances in higher layers • Timing: timing is improved. • Area cost: Fewer buffers needed. • Experiments demonstrate that one can achieve • Over 50% slack improvement (for worst slack and total slack) • 1% reduction in area and 4% reduction in wirelength

  4. 2X 1X Layer Assignment Problem for cu65 4X

  5. IP IP An Awakening in the Designer Community

  6. Cu65HP Metal RC Characteristics

  7. Expected distances between Buffers for cu65 1. A buffer can drive longer (2x-3.5x) distance in higher layers with better delay 2. Fewer buffers needed • Created a very long 2-pin net for cu65 • Ran buffopt using each buffer from the library in turn

  8. Buffering on Different Layers (M2, B1, EA)

  9. Two Main Algorithms • New buffering for electrical correction algorithm • LASR (Layer Assignment for Slew Recovery) • Idea: when a route goes over a blockage, bump wire up to higher layer if needed to meet slew target. • New buffering for delay optimization on critical nets • LADY (Layer Assignment for Delay) • Idea: during buffering, bump up a subnet to the next higher layer and accept solution if it significantly improves slack

  10. LASR – Layer Assignment for Slew Recovery • When crossing a blockage, if the slew constraint cannot be met, bump the subnet up to the higher layers. • Advantages: • Fast, can be used with Van Ginneken’s framework • No tricky cost function • Uses minimum high wire resources

  11. Candidate solutions are propagated toward the source Overview of Algorithm • Start from sinks • Candidate solutions are generated • Three operations • Add Wire • Insert Buffer • Merge • Solution Pruning

  12. Solution Propagation: Add Wire • c2 = c1 + cx • s2 = s1 + (rcx2/2 + rxc1)·ln9 • s: slew degradation along wires • r: wire slew resistance per unit length • c: wire capacitance per unit length x (v1, c1, w1, s1) (v2, c2, w2, s2)

  13. Solution Propagation: Insert Buffer (v1, c1, w1, s1) (v1, c1b, w1b, s1b) c1b = Cb s1b = 0 w1b = w1+w(b) Cb: buffer input capacitance Pruned if the following slew constraint is violated. If no solution can satisfy the slew constraint, bump the subnet to the next higher layer and compute the solution which satisfies the slew constraint and with minimum cost.

  14. Solution Propagation: Merge • cmerge = cl + cr • wmerge = wl + wr • smerge = max(sl , sr) (v, cr ,wlr,sr) (v, cl , wl , sl)

  15. Solution Pruning • Two candidate solutions • Solution 1: (v, c1, w1 , s1) • Solution 2: (v, c2, w2 , s2) • Solution 1 is inferior if • c1 > c2 : larger load • and w1 > w2 : larger buffer area • and s1 > s2 : worse cumulative slew degradation on wire

  16. LASR Example Slew constraint still can not be met. Slew constraint can not be met, so bump up to the higher layer.

  17. LADY – Layer Assignment for Delay • Idea: Use traditional Van Ginneken’s algorithm, but pick a fatter wire if it buys you X ps improvement. • X is tunable parm, e.g., 5-500 ps • Guarantees only long nets get promoted to thick metal • No complicated user-specified cost function • Small runtime overhead (5%)

  18. Solution Propagation: Insert Buffer (v1, c1, w1, q1) (v1, c1b, w1b, q1b) c1b = Cb q1b = q1-RbC1 w1b = w1+w(b) Cb: buffer input capacitance Rb: buffer driving resistance Bump the subnet to the next higher layer if it can obtain X ps improvement.

  19. Delay 18 ps 8 ps 3 ps 28 ps 8 ps Delay 10 ps Delay 7 ps Delay 50 ps Delay 22 ps Delay 14 ps LADY Example (X = 5 ps)

  20. Experiment results • Experiments on XPP Top in Cu65 technology (6 layers)

  21. Observation • LADY+LASR improves (for the whole PDS) • FOM by 63% • Worst Slack by 52% • Area by 1% • Wirelength by 4%

  22. Benefits • Two buffering techniques considering layer assignment: LASR and LADY • LASR+LADY can obtain • Over 50% slack improvement (for worst slack and total slack) • 1% reduction in area and 4% reduction in wirelength

  23. Bus design • Bundles of signals treated symmetrically • Identical electrical/physical environment for each bit • Need to consider synchronization • Abstraction of communication during early design • Often integrated with floorplanning • Global busses often pre-designed prior to detailed block implementation (esp. in microprocessors)

  24. Congestion considerations • Designs increasingly wire-limited • Interconnect optimization: routing resource intensive • spacing, wide-wires, up-layering • Congestion can cause detours (or even unroutable designs) • Detours increase interconnect delay as well as interconnect delay unpredictability • Wire delay models during tech-mapping, placement are based on shortest path routing • Detours increase convergence problems because of poor upstream wire delay modeling

  25. References • J. Cong and L. He, “Theory and algorithm of local refinement based optimization with application to device and interconnect sizing”, IEEE Trans. CAD, pp. 406-420, Apr. 1999. • J. Cong, “An interconnect-centric design flow for nanometer technologies,” Proc. IEEE, pp. 505-528, April 2001. • J. Lillis, C.-K. Cheng, T.-T. Lin, and C.-Y. Ho, “New performance-driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing”, Proc. DAC, pp. 395-400, June 1996. • M. Hrkic and J. Lillis, “S-tree: A technique for buffered routing tree synthesis”, Proc. DAC, pp. 98-103, June 2002. • L. van Ginneken, “Buffer placement in distributed RC-tree networks for minimal Elmore delay”, Proc. ISCAS, pp. 865-868, 1990. • C. Alpert, M. Hrkic, J. Hu, and S. Quay, “Fast and flexible buffer trees that navigate the physical layout environment”, Proc. DAC, pp. 24-29, June 2004. • M. Becer, R. Vaidyanathan, C. Oh, and R. Panda, “Crosstalk noise control in an SoC physical design flow”, IEEE Trans. CAD, pp. 488-497, Apr. 2004.

More Related