Interconnect Working Group

1. Interconnect Working Group 2012 Winter Update December 2012 Hsinchu, Taiwan

2. ITWG Regional Chairs Korea Gil-HeyunChoi Noh-Jung Kwak Europe Hans-Joachim Barth Alexis Farcy Japan Tomo Nakamura Hideki Shibata US Paul Zimmerman Azad Naeemi Taiwan Winston Shue

3. List of Contributors Sang HoonAhn Lucile Arnaud Koji Ban Tien-I Bao Hans-Joachim Barth Eric Beyne Boyan Boyanov Jon Candelaria GilheyunChoi Mike Corbett Alexis Farcy Paul Feeney Philip Garrou Climbing Huang Takashi Hayakawa Paul H Diane Hymes Shi-PuuJeng Masayoshi Imai AtsunobuIsobayashi Shin-PuuJeng MorihiroKada Sibum Kim Nobuyoshi Kobayashi Kaushik Kumar NohjungKwak Hanchoon Lee Didier Louis James Lu David Maloney Akira Matsumoto Azad Naeemi MehulNaik • Tomoji Nakamura • Yuichi Nakao • Sunil Patel • SeshRamaswami • Urmi Ray • Rick Reidy • Mark Scannell • Hideki Shibata • Winston Shue • Michele Stucchi • Manabu Tsujimura • Zsolt Tokei • Kazuyoshi Ueno • Osamu Yamazaki • Jaeyoung Yang • Paul Zimmerman

4. Interconnect scope Conductors and dielectrics Starts at contacts Metal 1 through global levels Includes the pre-metal dielectric (PMD) Associated planarization Necessary etch, strip and cleans Embedded passives Global and intermediate TSVs for 3D Reliability, system, and performance issues “Needs” based replaced by scaled, equivalently scaled or functional diversity drivers.

5. Interconnect Relevance ~ Energy per Operation ~ Interconnects Source: Paul Franzon, NC State Univ.

6. Wire Wire Wire Metal 3 Via Via Via Metal 2 Metal 1 Metal 0 Poly Pitch Metal 1 Pitch Metal 1 Pitch Metal 1 Pitch Hierarchical Cross Sections ASIC Cross-Section Flash Cross-Section MPU Cross-Section Passivation Dielectric Etch Stop Layer Global (=IMx1.5~2µm) Dielectric Capping Layer Global (=IMx1.5~2µm) Copper Conductor with Barrier / Nucleation Layer Semi- Global (=M1x2) Inter- Mediate (=M1x1) Inter- Mediate (=M1x1) Tungsten Contact Plug Metal 1 Metal 1 Pre-Metal Dielectric • MPU: Revised hierarchy • ASIC: No drastic change, however semi-global should be kept at 2 x M1 • Flash: The current technology driver for M1

7. Technology Requirements General requirements Resistivity Dielectric constant Metal levels Reliability metrics Level specific requirements (M1, intermediate, global) Geometrical Via size and aspect ratio Barrier/cladding thickness Planarization specs Materials requirements Conductor effective resistivity and scattering effects Electrical characteristics Delay, capacitance, crosstalk, power index To be extended, where possible, to the 3D section Propose to add resistance/length

8. Technology Drivers Expanding Traditional geometric scaling Cost Necessary to enable transistor scaling Pitch division Performance Dielectric constant scaling for delay, and power improvements Crosstalk (capacitive coupling factor) Reliability EM TDDB Increasing value by adding functionality using CMOS-compatible solutions: 3D, optical components, sensors Contributing to More than Moore

9. 4.0 3.5 3.0 Effective Dielectric Constant; keff 2.5 2.0 1.5 1.0 2012 Low-k Roadmap Update Calculated based on delay time using typical critical path ITRS2009 Estimated by typical three kinds of low-k ILD structures 2.82-3.16 ITRS2011-12 ITRS2009-10 ITRS2007-8 2.55-3.00 2.40-2.78 2.40-2.78 2.15-2.46 2.15-2.46 1.88-2.28 1.88-2.28 1.65-2.09 1.65-2.09 Delay time improvement by 20% Delay time improvement by 20% Manufacturable solutions are known Manufacturable solutions exist, and are being optimized Red Brick Wall (Solutions are NOT known) 19 20 21 12 13 14 15 16 17 18 22 23 24 25 26 27 Year of 1st Shipment

10. Difficult Challenges (1/2) Meeting the requirements of scaled metal/dielectric systems Managing RC delay and power New dielectrics (including air gap) Controlling conductivity (liners and scattering) Filling small features Barriers and nucleation layer Conductor deposition Reliability Electrical and thermo-mechanical Engineering a manufacturable interconnect stack compatible with new materials and processes Defects Metrology Variability

11. Difficult Challenges (2/2) Meeting the requirements with equivalent scaling Interconnect design and architecture (includes multi-core benefits) Alternative metal/dielectric assemblies 3D with TSV Interconnects beyond metal/dielectrics Optical wiring Carbon or non-carbon emerging materials Reliability Electrical and thermo-mechanical Engineering a CMOS-compatible manufacturable interconnect system Non-traditional materials (for optical, CNT etc.) Unique metrology (alignment, chirality measurements, turning radius etc)

12. DP options: LELE and SADP • LELE (Litho-Etch, Litho-Etch) option: 2 exposure steps with different masks; each exposure step is followed by an etch step • SADP (Self Aligned Double Patterning) option: trenches are defined by spacers formed at the sides of sacrificial material patterned with double target pitch; after removing the sacrificial material, the spacers allow to etch trenches at the target pitch [*] Stucchi et al, IMEC, IITC 2012

13. Potential issues • LELE option: two independent patterning steps aligned to each other • CD and overlay variations between DP lines A and B • Consequent impact on wire electrical parameters: unbalance of resistance (RARB) and capacitance (CABCBA) • SADP option: two patterning steps self-aligned to each other • CD variations between DP lines A and B; no overlay • Consequent impact on wire electrical parameters: unbalance of resistance (RARB) [*] Stucchi et al, IMEC, IITC 2012

14. Example of maximum variations with reference to nominal values RACA CAB/Cwire CBA/Cwire RBCB AB AB • LELE, SADP and EUV are compared in simulations [*] • CD variations ~+/- 3%, Overlay variations in LELE ~ +/- 7nm • AB = max. % unbalance between A and B OL= 0nm OL= 0nm OL=+7nm OL=+7nm OL= 0nm OL= 0nm OL= -7nm OL= -7nm OL= 0nm OL= 0nm Max. RC Delay Max. Coupling % % • LELE and SDDP require tight CD control for reducing the unbalance in RC (LELE: 84%; SDDP: 53%) • LELE requires also tight overlay CD control for reducing the max. unbalance in coupling capacitance (111% coupling in the case study) [*] Stucchi et al, IMEC, IITC 2012

15. Interconnect architecture M2 M2 • Both via-via (d) and via-metal (x) spaces are affected by variations in registration, lithography exposure, and pattern transfer • ILD must withstand applied fields enhanced by process variations V2 V1 M1 V1 d M1 M1 x V1 V0 x

16. Time Dependent Dielectric Breakdown:Sources of Process Variation Source: Rod Augur, Global Foundries

17. Implications for dielectrics M2 • Typical mis-registration design rules allow at least 50% unlandedness (x/s ≤ 0.5) • Stress fields will exceed 2MV/cm within the next few technology generations V1 M1 M1 x s

18. Challenge: Line Resistance Scaling Limit for Metal ALD Barrier • Barrier volume becomes significant. • Cu resistivity increases exponentially with scaling. 10nm Opportunity: Develop new deposition methods that enable film scaling to < 1nm Source: James Clarke and Boyan Boyanov, Intel Corp. Barrier / Liner/ Copper

19. Emerging Electrical Interconnects: Multi-Layer Graphene Interconnects It is essential to have smooth edges to beat copper wires. Top contacts are less effective in utilizing the lower graphene layers. Source: Azad Naeemi, GA Tech

20. Interconnects for Emerging Post-CMOS Switches: Spin Interconnects W = 7.5 nm Gate pitch = 140 nm Interconnects for most novel state variables are inherently slow. To achieve the same performance (Speed), interconnects for emerging devices must be shorter. Shorter interconnects may be achieved if novel devices have smaller footprints or fewer devices are needed for the same task. Spin diffusion Spin waves (νSWB=104 m/s) Spin waves (νSWB=105 m/s) Spin Drift Spin ballistic CMOS 5X CMOS 1X Source: Azad Naeemi, GA Tech

21. Emerging Interconnect Changes • Current focus is on transport properties of Cu replacements, optical and native device interconnects • Research focus in optical in on die-to-die and chip-chip as the most probable commercial intercept • Rate of introduction of new candidates in research is decreasing  topological insulators topic was the only 2011 new addition • Key messages: • New materials needed for local/intermediate interconnects to address reliability and energy issues, but few new options seen, especially for dielectrics • The overall interconnect challenges cannot be met with new materials only - co-design with new architectures and emerging devices must also occur for sustainable solutions