Digital Design – Optimizations and Tradeoffs

1. Digital Design – Optimizations and Tradeoffs Chapter 6 - Optimizations and Tradeoffs

2. Digital DesignOptimizations and Tradeoffs Figure 6.1 A circuit transformation that improves both size and delay, i.e., an optimization.

3. Digital DesignOptimizations and Tradeoffs Figure 6.2 A circuit transformation that improves size but worsens delay, i.e., a tradeoff.

4. Digital DesignOptimizations and Tradeoffs Figure 6.3 Optimizations (left) versus tradeoffs (right).

5. Digital DesignOptimizations and Tradeoffs Figure 6.4 Three-variable K-map.

6. Digital DesignOptimizations and Tradeoffs Figure 6.5 Minimizing a three-variable function using a K-map.

7. Digital DesignOptimizations and Tradeoffs Figure 6.6 Four adjacent 1s. Figure 6.7 Non-optimal circles.

8. Digital DesignOptimizations and Tradeoffs Figure 6.8 Four adjacent 1s. Figure 6.9 Circling a 1 twice.

9. Digital DesignOptimizations and Tradeoffs Figure 6.10 An unnecessary term. Figure 6.11 Sides are adjacent.

10. Digital DesignOptimizations and Tradeoffs Figure 6.12 Invalid circle. Figure 6.13 Four adjacent 1s.

11. Digital DesignOptimizations and Tradeoffs Figure 6.14 Four-variable K-map.

12. Digital DesignOptimizations and Tradeoffs Figure 6.15 Eight adjacent cells.

13. Digital DesignOptimizations and Tradeoffs Figure 6.16 w’xz and yz terms.

14. Digital DesignOptimizations and Tradeoffs Figure 6.17 Terms on the K-map. Figure 6.18 A cover.

15. Digital DesignOptimizations and Tradeoffs Figure 6.19 K-map example.

16. Digital DesignOptimizations and Tradeoffs Figure 6.20 Map with don’t cares. Figure 6.21 Wasteful use of X’s.

17. Digital DesignOptimizations and Tradeoffs Figure 6.22 Sliding switch example. Figure 6.23 Without don’t cares. Figure 6.24 With don’t cares.

18. Digital DesignOptimizations and Tradeoffs Figure 6.25 A cover is not necessarily optimal -- the top cover uses more terms.

19. Digital DesignOptimizations and Tradeoffs Figure 6.26 Implicants. Figure 6.27 Essential prime-implicants.

20. Digital DesignOptimizations and Tradeoffs Table 6.1 Heuristic for two-level logic size optimization starting with a K-map.

21. Digital DesignOptimizations and Tradeoffs Figure 6.28 All prime implicants (top); including essential prime implicants in the cover (middle); covering remaining 1s (bottom).

22. Digital DesignOptimizations and Tradeoffs Figure 6.30 Multi-level logic to tradeoff performance and size: (a) two-level circuit, (b) multi-level circuit with fewer transistors, (c) illustration of the size versus delay tradeoff. Numbers inside gates represent transistor counts.

23. Digital DesignOptimizations and Tradeoffs Figure 6.31 Multi-level logic to tradeoff performance and size: (a) two-level circuit, (b) multi-level circuit with fewer transistors, (c) tradeoff of size vs. delay. Numbers inside gates represent transistor counts.

24. Digital DesignOptimizations and Tradeoffs Figure 6.32 Multi-level optimization that reduces size without increasing delay, by altering a non-critical path: (a) original circuit, (b) new circuit with fewer transistors but same delay, (c) illustration of the size optimization with no tradeoff with delay.

25. Digital DesignOptimizations and Tradeoffs Figure 6.33 Eliminating redundant states.

26. Digital DesignOptimizations and Tradeoffs Figure 6.34 Laser timer state diagram with alternative binary state encoding.

27. Digital DesignOptimizations and Tradeoffs Table 6.2 State table for laser timer controller with alternative encoding.

28. Digital DesignOptimizations and Tradeoffs Figure 6.35 FSM for given sequence.

29. Digital DesignOptimizations and Tradeoffs Table 6.3 State table using binary encoding. Table 6.4 State table using one-hot encoding.

30. Digital DesignOptimizations and Tradeoffs Figure 6.36 One-hot encoding can reduce delay: (a) minimum binary encoding, (b) one-hot encoding, (c) though total sizes may be roughly equal (one-hot encoding uses fewer gates but more flip-flops), one-hot yields a shorter critical path.

31. Digital DesignOptimizations and Tradeoffs Figure 6.37 One-hot encoding of laser timer.

32. Digital DesignOptimizations and Tradeoffs Table 6.5 State table for laser timer controller with one-hot encoding.

33. Digital DesignOptimizations and Tradeoffs Figure 6.38 FSM for given sequence.

34. Digital DesignOptimizations and Tradeoffs Figure 6.39 Sequence generator FSM.

35. Digital DesignOptimizations and Tradeoffs Table 6.6 Partial state table for sequence generator controller using output encoding.

36. Digital DesignOptimizations and Tradeoffs Figure 6.40 Sequence generator controller with output encoding.

37. Digital DesignOptimizations and Tradeoffs Figure 6.41 Standard controller architecture -- general view.

38. Digital DesignOptimizations and Tradeoffs Figure 6.42 Moore (a) versus Mealy (b) FSM controller architectures.

39. Digital DesignOptimizations and Tradeoffs Figure 6.43 A Mealy FSM associates outputs with transistions, not states.

40. Digital DesignOptimizations and Tradeoffs Figure 6.44 Capturing desired behavior using a: (a) Moore FSM, (b) Mealy FSM.

41. Digital DesignOptimizations and Tradeoffs Figure 6.45 4-bit carry-ripple adder, with the longest path (the critical path) shown.

42. Digital DesignOptimizations and Tradeoffs Figure 6.46 8-bit adder built from two 4-bit adders.

43. Digital DesignOptimizations and Tradeoffs Figure 6.47 Adding two binary numbers by a naive inefficient carry lookahead scheme -- each stage looks at all earlier bits and computes whether the carry-in bit to that stage would be a 1.

44. Digital DesignOptimizations and Tradeoffs Figure 6.48 Adding two binary numbers using a fast carry-lookahead scheme.

45. Digital DesignOptimizations and Tradeoffs Figure 6.48 Adding two binary numbers using a fast carry-lookahead scheme. (cont.)

46. Digital DesignOptimizations and Tradeoffs Figure 6.49 High-level view of a 4-bit carry-lookahead adder.

47. Digital DesignOptimizations and Tradeoffs Figure 6.50 Gate size problem.

48. Digital DesignOptimizations and Tradeoffs Figure 6.51 16-bit adder implemented using four 4-bit adders connected in a carry-ripple manner.

49. Digital DesignOptimizations and Tradeoffs Figure 6.52 16-bit adder implemented using four CLA 4-bit adders and a second level of lookahead.

50. Digital DesignOptimizations and Tradeoffs Figure 6.53 Simplified view of multi-level carry-lookahead, showing tree structure, which enables fast addition with reasonable numbers and sizes of gates. Each level adds only two gate-delays.