FFT COMPONENTS PROJECT Final Design Review

1. FFT COMPONENTS PROJECTFinal Design Review / December 12, 2005 TEAM MEMBERS: Scott Crawford (Leader) Jon Oppelaar

2. Outline Project Overview Goals Background Info Specifications Progress Components Function Logic Diagrams Simulation Waveforms Physical Layout Process Layout Options Diagrams LVS Confirmation Padframe Evaluation Issues / Improvements Final Thoughts Looking Ahead References Special Thanks

3. Project Goals Support stage 4 of the fingerprint authenticator project Create 16-bit complex multiplier and adder for use in FFT algorithm Use VLSI technology to create an Application-Specific Integrated Chip (ASIC) to submit for fabrication Document and present results

4. Background Info Multiplier - A 16 bit complex multiplier that is synchronous, triggered on a rising edge of the system clock.  Adder - A 16 bit adder Butterfly � Radix-4, consists of multipliers, adders and a twiddle factor memory Input/ Output Interface - FFT algorithm requires the entire sequence of input samples to be provided on its input port in order to initiate the operation. START and DONE signals should be available.

5. Project Specifications 100 MHz clock speed is desired Algorithm radix-4 Arithmetic: 16 bit fixed point, 2�s complement Pipelining of complex arithmetic operations if 100MHz not possible Identical standards for all control and status signals Clock input (CLK) and reset (RST) Arithmetic operators contain an overflow status line (OVFL)

6. Project Strategy Make a tentative schedule of tasks to keep progress at a steady rate Research topics and technical data needed in order to build components For all components, follow these steps: Sketch drafts of design as a gate level schematic Design schematic on Mentor Graphics software (CAD) Simulate and test component using SPICE based simulation Correct and verify functionality (create block symbol if necessary) Create physical layout of final transistor-level multiplier component Correct all LVS and DRC-related issues and errors Create padframe layout for MOSIS fabrication Use Mach-TA to determine timing data for circuit Submit layout to MOSIS Confirm functionality of IC when received back from MOSIS Create presentation for completed project

7. Collaboration Log 9/18/2005 Begin research and decide tasks that need to be completed. 9/25/2005 Figure out Boolean logic and begin creating gate level schematic. 10/11/2005 Continue designing gate level schematic for adder circuit. Write first pre-report for project leader. 10/14/05 Begin designing half-adder design in software 10/17/05 Finish half-adder design and begin full-adder design in software 10/24/2005 Finishing full-adder design in software and prepare for PDR presentation 10/31/2005 Create 8-bit adder circuit using single-bit full-adder blocks 11/2/2005 Simulate 8-bit adder design, confirm functionality 11/3/2005 Begin 4-bit multiplier design 11/7/2005 Implement 4-bit multiplier design 11/11/2005 Continue working on 4-bit multiplier 11/13/2005 Simulate 4-bit multiplier

8. Collaboration Log (2) 11/14/2005 Add 2s compliment functionality to multiplier 11/15/2005 Create 8-bit subtractor and simulate circuit 11/16/2005 Create complex multiplier in software and simulate circuit Update documentation and create presentation for upcoming CDR 11/18/2005 Create buffers for multiplier to synchronize circuit 11/22/2005 Simulate multiplier circuit with buffers Generate screen shots of simulation results for all components 11/28/2005 Begin physical layout of complex multiplier circuit 11/29/2005 Begin Debugging DRC and LVS errors from physical layout 12/4/2005 Begin padframe layout and auto-routing to pins 12/6/2005 � 12/9/2005 Manually route padframe to layout Finish fixing DRC errors from padframe 12/9/2005 � 12/12/05 Gather information and create presentation for FDR

9. Task Assignments Tasks divided between implementation and documentation Jon: Transistor and physical layouts in CAD, debugging, component integration Scott: Scheduling, logs, reports, presentations, data collecting Consistent collaboration and progress updating within team Shared responsibilities for circuit design, simulation and verification

10. Current Project Progress

11. Project Components

12. Single-Bit Half-Adder Adds two bits together with a sum and carry output Used to optimize partial product calculations in 4-bit multipliers Building block for full-adder

13. Single-Bit Half-Adder SCHEMATIC

14. Single-Bit Half-Adder SIMULATION WAVEFORM

15. Single-Bit Full-Adder Adds three one-bit inputs and outputs a sum and a carry Similar to half-adder, but has an input carry bit Consists of two half-adders connected with an OR gate Vital component in multiplier circuit Cascaded full-adders used to create an 8-bit adder

16. Single-Bit Full-Adder

17. Single-Bit Full-Adder

18. 8-Bit Full-Adder Consists of eight cascaded, single-bit full adders �Carry� bit is traversed through the circuit Used in complex multiplier arithmetic calculation

19. 8-Bit Full-Adder Fig. A - Cascaded single-bit full-adders form an 8-bit full-adder Fig. B - The 8-bit adder represented as a block symbol

20. 8-Bit Full-Adder Uses negative and positive numbers with a transition of the carry bit to show 2s compliment Input A: 00111000 (+56 in decimal)Input B: 11101011 (-21 in decimal)Expected SUM: 00100011 (+35 in decimal, CarryIN=0)

21. The waveforms show that the SUM is indeed 00100011 (+35) 8-Bit Full-Adder

22. Single-Bit Full-Subtractor Takes in three one-bit inputs: A, B, and �Borrow In� Subtracts B from A, outputs the difference and a �Borrow Out� bit Same circuitry as full-adder except for an extra inverter, since borrow and carry are inverse operations Component is needed to create complex multiplier

23. Single-Bit Full-Subtractor

24. Single-Bit Full-Subtractor

25. 8-bit Full-Subtractor Identical design to 8-bit full-adder Consists of eight cascaded, single-bit full subtractors �Borrow� bit is traversed through the circuit Used in complex multiplier arithmetic calculation

26. 8-bit Full-Subtractor Fig. A - Cascaded single-bit full-subtractors form an 8-bit full-subtractor Fig. B - The 8-bit subtractor represented as a block symbol

27. 8-bit Full-Subtractor Uses negative and positive numbers with a transition of the carry bit to show 2s compliment and carrying functionalities Input A: 00111000 (+56 in decimal)Input B: 11101011 (-21 in decimal)Expected DIFF: 00100011 (+77 in decimal, BorrowIN=0)

28. The waveforms show that the DIFF is indeed 01001101 (+77) 8-bit Full-Subtractor

29. 4-bit Multiplier Must work for 2s compliment numbers and be able to multiply two 4-bit inputs Uses arrays of �AND� gates to generate partial products and a sequence of adders to sum them together To multiply two n-bit numbers, n� �AND� gates required 4� = 16 �AND� gates n�-n adder blocks required 4�-4 = 12 adder blocks required Product is length 2n 2*4 = 8-bit product

30. 4-bit Multiplier To convert into 2s compliment, all �AND� gates containing sign bits are inverted Final sign bit output also inverted To optimize, half-adders can replace full-adders on right-most position in partial products (since no carry input exists)

31. 4-bit Multiplier

32. 4-bit Multiplier Used negative and positive numbers to show 2s compliment functionality Input A: 1111 (-1 in decimal)Input B: 0111 (+7 in decimal)Expected PRODUCT: 11111001 (-7 in decimal)

33. 4-bit Multiplier The waveforms show that the PROD is indeed 11111001 (-7)

34. Complex Multiplier Capable of multiplying two 8-bit complex numbers Splits outputs into real and imaginary products Each output is 8-bits with each with an overflow bit Makes use of previous components in design

35. Complex Multiplier

36. Complex Multiplier

37. Complex Multiplier Project specifications require multiplier to run 100 MHz or higher Delay needs to be under 10ns Max delay is measured as the time between the first input and the final output

38. Complex Multiplier Max delay = 4.816 ns

39. Complex Multiplier Use of buffers on inputs and outputs allows for multiplier to be synchronous on a clock pulse Reduces noise in the data User has more control of circuit Ability to set speed of circuit using clock Reset capability

40. Complex Multiplier Consist of eight D-latches connected to single reset and clock pins Inverters placed on outputs to correct inverted QB output on latches Input cannot be sent faster than the clock speed, otherwise errors will occur

41. Complex Multiplier

42. Complex Multiplier Given the following inputs: A: 1001 (-7 in decimal) B: 1010 (-6 in decimal) C: 1001 (-7 in decimal) D: 1010 (-6 in decimal) The output should return: (AC - BD) + (AD + BC) j (49 � 36) + (42 + 42) j 13 (real) + 84 (imag.)

43. Complex Multiplier The real and imaginary outputs: R: 00001101 (+13 in decimal) I: 01010100 (+84 in decimal) This is the correct answer for the given inputsAlso note how the data is cleaner after adding the buffers (no spikes or noise)

44. Physical Layout Consists of two main tasks Converting transistor-level design to physical-level design Placing and routing physical layout onto padframe Using Mentor Graphics allows for greater compatibility Each step requires rule checking and debugging Choice of auto or manual (custom) layouts We chose auto-layout for the physical-layer design and manual layout for routing the padframe

45. Physical Layout Auto layout lets software generate the physical layout Manual layout requires the user to create the physical layout from scratch Pros/Cons of auto-layout Pros Saves time � quickly created by Mentor Graphics Software has more knowledge about design rules Cons Software does not use good space-saving techniques Layout not as optimal as user can make it

46. Physical Layout

47. Physical Layout

48. Physical Layout

49. Physical Layout

50. Evaluation Time constraints caused the project to have limitations Potential improvements in our design More research on better full-adder designs, such as carry-select and carry-bypass Better methods to calculate complex multiplication Use D-flip-flops instead of D-latches Simulations took long periods of time to complete

51. Evaluation Successful and rewarding project Gained knowledge of full ASIC design process using VLSI Good experience working as a team Better understanding of the complexities of chip design

52. Looking Ahead� Complete layout testing in MACH-TA Submit design to MOSIS for fabrication Complete final design review report Test chip (April 2006), verify functionality and record results Prepare for project presentation in May 2006

53. References Logic Gates http://isweb.redwoods.cc.ca.us/INSTRUCT/CalderwoodD/diglogic/index.htm 3-input XOR Logic http://www.shef.ac.uk/physics/teaching/phy107/othergates.html 8-bit adder notes http://www.ece.arizona.edu/~ece274/lectures/lecture9.pdf Full and half-adders http://www.phys.ualberta.ca/~gingrich/phys395/notes/node129.html 4-bit multiplier info http://www-mount.ee.umn.edu/~sobelman/papers/kavitha_iscas04.pdf 2s compliment multiplier http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Multip.htm 2s compliment http://www.evergreen.edu/biophysics/technotes/program/2s_comp.htm UNH ECE 715/815 http://ece.unh.edu/courses/ece715 ASIC Design Kit (ADK) Documentation and Tutorials http://www.mentor.com/partners/hep/AsicDesignKit/Docpage.html

54. Special Thanks PROF. ANDRZEJ RUCINSKI � for helping us through the design process FRANK HLUDIK � for his endless help in the design automation lab EVERYONE IN ECE 715 � for their open cooperation with project issues MENTOR GRAPHICS � for use of their Electronic Design Automation (EDA) software MOSIS � for funding our chip fabrication