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Explore the methodology, results, and implications of a study on FPGA leakage power reduction and implications for mobile applications, presented at IEEE Custom Integrated Circuits Conference in 2003.
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Leakage Power Analysisof a 90nm FPGA Published at IEEE Custom Integrated Circuits Conference in 2003 Authors: Tim Tuan (Xilinx), Bocheng Lai (UCLA) Presenter: Sang-Kyo Han (ECE, University of Maryland)
My Motivations for Paper Selection • I have an interest on FPGA power reduction. • I want to know the reference data about leakage power of FPGA and the measurement method of it.
Contents • Introduction • Background • Methodology • Result and Analysis • Conclusions
Introduction • FPGAs have become attractive implementation solutions. • Promising solutions for applications that require both performance and flexibility • Motivations of the Research • To support reconfigurations, FPGAs use more transistors than • fixed-logic solutions, resulting in higher leakage power. • FPGA due to excessive leakage is unsuitable for mobile applications. • Methodology based on device-level simulations using • BSIM4 models • BSIM4 models include a number of leakage-modeling • improvements over prior versions. • Significant power reduction from analysis is possible.
Background – Existing Work • Leakage power has been extensively studied in ASICs and microprocessors. • Focus on FPGA dynamic power consumption • E. Kusse, J.Rabaey [ISLPED,1998] • L. Shang [FPGA,2002] • K. Poon [FPL,2002] • Current data on FPGA leakage by commercial vendors • Limited to worst-case data points • Provide no details or understanding of the underlying issues
Background – Architectural Model (1) • 1.2V, SRAM-based FPGAs built in a 90nm CMOS process • Modern FPGA architecture is composed of CLBs, I/O blocks, clock managers, block RAMs and multipliers. • This study focuses on the CLB array. • CLB is the representative of smaller or embedded FPGAs, which are more suitable for mobile application. CLB: Configurable Logic Block
Background – Architectural Model (2) • CLB consists of interconnect switch matrix and four logic slices. • Switch matrix is composed of a set of switches, each implemented with configurable multiplexors. • OXBAR and IXBAR select CLB outputs and inputs, respectively. DOUBLE connect CLBs that are two blocks apart. • Each logic slice consists of two 4-input look-up tables (LUTs) and two flip-flops (FFs).
Methodology – Overall • SPICE simulation using BSIM4 device models • For sub-100nm devices, BSIM4 provides improvements in leakage modeling. • Focus on a single CLB design since all CLBs in an FPGA are identical • Each smaller block in CLB is simulated individually to identify its leakage power consumption. • Total leakage power of CLB array = (∑ block leakages) * (# of CLBs)
Methodology – Input Data • Leakage power of a circuit depends on the values of its inputs. • Leakage varies by more than 4X depending on the values of inputs. • To model effects of input data variation, each block is simulated under all possible input states. • For each block, its minimum, maximum and average leakage with respect to input data under best-, worst- and average-case design data, respectively, are stored.
Methodology – Resource Utilization • Designs implemented in FPGAs never use all available resources. • FPGA provides an excess routing resources to ensure the efficient mapping and routing of most designs. • Typically, the utilization of interconnect resources is low, but for logic blocks is relatively high. • TABLE 1: from survey of customer designs • Resource utilization affects total leakage power. • A block consumes less leakage power when unused. • Unused LUT stores all 0’s by default. • Each block is simulated in both used and unused configurations.
Result – FPGA Leakage • At 25̊C, the FPGA consumes 4.2uW per CLB, which means a 1000-CLB FPGA would consume approximately 4.2mW. • At 85̊C, 18.9uW per CLB due to the exponential temperature dependency of subthreshold leakage • GSM cell phone’s standby current budget for digital baseband processing is 300uA. • A 300uA upper bound on leakage power would imply a limit of 86 CLBs at 25̊C , and 20 CLBs at 85̊C, which means too small sizes to perform significant processing.
Result – Design Dependency • For best- and worst-case data conditions, the degree of variation from the typical case is ±13% at 25̊C. • For CLB utilization factors of 50% and 100%, leakage power varies by no more than ± 6%, which means non-trivial leakage in unused resources. • For a design with worst-case data, 100% CLB utilization, at 85̊C is 26uW per CLB, 37.6% higher than average.
Result – Circuit-based Breakdown • In an FPGA, the three most common circuit types are configuration SRAM cells, interconnect multiplexors and LUTs. • These three circuit types consume 88% of the total leakage power. • The configuration SRAM cells consume 38% of the total leakage. • Using high-Vth, thick-oxide transistors can eliminate most of the SRAM leakage power, but will increase configuration time.
Result – Utilization-based Breakdown • The leakage consumption by the unused blocks is referred as unused leakage. • For a small design that uses 50% of the CLBs, unused leakage is 56% of the total leakage power. • For a design of 100% CLB utilization, unused leakage is still a significant portion (35%) of the total. • This amount is consumed entirely in unused interconnect switches. • FPGA CAD tools can help maximize the savings by grouping unused resources such that they can be collectively powered down.
Conclusions • The results quantified the nominal leakage power of the FPGA and the variation due to design-specific parameters. • The FPGA consumes 4.2uW per CLB nominally, and more than 26uW per CLB in the worst-case conditions. • To enable deployment of FPGAs in mobile applications, significant leakage power reduction is needed. • The results indicated potential for substantial leakage reduction.
