ECE 667 Spring 2007 Synthesis and Verification of Digital Circuits

1. ECE 667Spring 2007Synthesis and Verificationof Digital Circuits Design Implementation

2. Digital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Standard Cells Pre-diffused Pre-wired Ma cro Cells Compiled Cells (Gate Arrays) (FPGA's) Implementation Choices ECE 667 - Synthesis & Verification - Implementation

3. The Custom Approach Intel 4004 ECE 667 - Synthesis & Verification - Implementation Courtesy Intel

4. Intel 4004 (‘71) Intel 8080 Intel 8085 Intel 8486 Intel 8286 Transition to Automation and Regular Structures ECE 667 - Synthesis & Verification - Implementation Courtesy Intel

5. Intel Pentium (IV) microprocessor ECE 667 - Synthesis & Verification - Implementation

6. Cell-based Design (or standard cells) Routing channel requirements are reduced by presence of more interconnect layers ECE 667 - Synthesis & Verification - Implementation

7. Standard Cell Layout Methodology – 1980s Routing channel VDD signals GND ECE 667 - Synthesis & Verification - Implementation

8. Standard Cell – The New Generation Cell-structure hidden underinterconnect layers ECE 667 - Synthesis & Verification - Implementation

9. Standard Cell - Example 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time ECE 667 - Synthesis & Verification - Implementation

10. Automatic Cell Generation Initial transistor geometries Placedtransistors Routedcell Compactedcell Finished cell ECE 667 - Synthesis & Verification - Implementation Courtesy Acadabra

11. Array-based Pre-diffused Pre-wired (Gate Arrays) (FPGA's) Array based design ECE 667 - Synthesis & Verification - Implementation

12. Gate Array — Sea-of-gates Uncommited Cell Committed Cell(4-input NOR) ECE 667 - Synthesis & Verification - Implementation

13. Sea-of-gate Primitive Cells Using oxide-isolation Using gate-isolation ECE 667 - Synthesis & Verification - Implementation

14. Product terms x x 0 1 x 2 AND OR plane plane f f 0 1 x x x 0 1 2 A Historical Perspective: the PLA ECE 667 - Synthesis & Verification - Implementation

15. Two-Level Logic Every logic function can beexpressed in sum-of-productsformat (AND-OR) minterm Inverting format (NOR-NOR) more effective ECE 667 - Synthesis & Verification - Implementation

16. Programmable Logic Array Pseudo-NMOS PLA V DD GND GND GND GND GND GND GND V X X X X X X f f 0 0 1 1 2 2 0 1 DD AND-plane OR-plane ECE 667 - Synthesis & Verification - Implementation

17. “Soft” MacroModules Synopsys DesignCompiler ECE 667 - Synthesis & Verification - Implementation

18. “Intellectual Property” A Protocol Processor for Wireless ECE 667 - Synthesis & Verification - Implementation

19. Design Capture Behavioral HDL Pre-Layout Simulation Structural Logic Synthesis Floorplanning Post-Layout Simulation Placement Physical Circuit Extraction Routing Tape-out Semicustom Design Flow Design Iteration ECE 667 - Synthesis & Verification - Implementation

20. The “Design Closure” Problem Iterative Removal of Timing Violations (white lines) Courtesy Synopsys ECE 667 - Synthesis & Verification - Implementation