ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits

Sep 16, 2012

220 likes | 360 Views

Share Presentation

Embed Code

Link

tariana

Download Presentation

ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

1. 1 ECE 667Spring 2011Synthesis and Verificationof Digital Circuits Boolean Functions and their Representations

ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits

ECE 667 - Synthesis

400 views • 23 slides

ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits

ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits. Introduction to Logic Synthesis. HDL specification. Front-end parsing. Techn-independent optimization. Technology mapping. Cell library. Manufacturing. Synthesis Flow . Logic synthesis . Specification. a. b.

481 views • 21 slides

ECE 667 Spring 2011 Synthesis and Verification of Digital Systems

ECE 667 Spring 2011 Synthesis and Verification of Digital Systems. Verification Introduction. Outline. Motivation: what is verification, why we need it Verification methods Formal methods Simulation-based functional verification Deterministic test generation.  ?. model. Design 1.

362 views • 16 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits

ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits. Boolean Functions and their Representations. Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003. B 0. B 1. B 2. B 4. The Boolean Space B n. B = { 0,1}, B 2 = {0,1} X {0,1} = {00, 01, 10, 11}.

386 views • 22 slides

ECE 667 Spring 2009 Synthesis and Verification of Digital Systems

ECE 667 Spring 2009 Synthesis and Verification of Digital Systems. Functional Decomposition. Slides adopted (with permission) from A. Mishchenko, 2003. Overview. The concept of functional decomposition Two uses of BDDs for decomposition as a computation engine to implement algorithms

367 views • 20 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Multi-level Logic Minimization Factored Forms. Slides adapted (with permission) from A. Kuehlmann, UC Berkeley 2003. Outline. Factored forms Motivation: multi-level logic representation Definitions, theory, examples

490 views • 32 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits

ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits. Scheduling Algorithms Analytical approach - ILP. Scheduling – a Combinatorial Optimization Problem. NP-complete Problem Optimal solutions for special cases and for ILP Integer linear program (ILP) Branch and bound

358 views • 23 slides

ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits

ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits. Boolean Functions and their Representations. Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003. B 0. B 1. B 2. B 4. The Boolean Space B n. B = { 0,1}, B 2 = {0,1} X {0,1} = {00, 01, 10, 11}.

329 views • 22 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits

ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits. Allocation Resource Binding & Sharing. Binding and Sharing Problem. Given: scheduled sequencing graph Operation concurrency well defined Consider operation types independently Problem decomposition (natural)

432 views • 30 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

Word-level (decision) Diagrams BMDs, TEDs. ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Outline. Review of design representations common representations of Boolean and arithmetic functions Motivation for word-level diagrams

452 views • 30 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Multi-level Minimization (Kernel-based). Slides adapted (with permission) from A. Kuehlmann, UC Berkeley, 2003. Multi-level Logic Transformation. Basic Operations on multi-level network: 1. Decomposition (single function)

482 views • 29 slides

ABC Logic Synthesis basics ECE 667 Synthesis and Verification of Digital Systems Spring 2011

ABC Logic Synthesis basics ECE 667 Synthesis and Verification of Digital Systems Spring 2011. Archana Rengaraj. Overview. Introduction Previous synthesis methods ABC synthesis And-Inverter Graphs (AIG) representation AIG canonicity and redundancy AIG construction NPN equivalence

678 views • 29 slides

ECE 667 Spring 2011 Synthesis and Verification of Digital Systems

ECE 667 Spring 2011 Synthesis and Verification of Digital Systems. FSM Traversal. O. X. (s,x). (s,x). s. s’. R. Finite State Machine (FSM) Model. FSM M(X,S, , ,O) Inputs: X Outputs: O States: S Next state function, (s,x) : S  X  S

236 views • 9 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. ABC System Combinational Logic Synthesis. Slides adapted from Alan Mishchenko, UC Berkeley 2010+. Outline. ABC System And-Inverter Graph (AIG) AIG construction AIG optimization Rewriting Substitution Redundancy removal

739 views • 54 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Binary Decision Diagrams (BDD). Outline. Background Canonical representations BDD’s Reduction rules Construction of BDD’s Logic manipulation of BDD’s Application to verification and SAT Reading:

471 views • 29 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Retiming. Retiming. Outline: Problem sequential synthesis Formulation Retiming algorithm. Optimizing Sequential Circuits by Retiming Gate-level Netlist. Netlist of gates and registers: Various Goals:

409 views • 24 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Technology Mapping for ASIC (standard cells). Slides adapted (with permission) from A. Kuehlmann, UC Berkeley 2003. Initial logic network. techn-independent optimization. technology mapping. Cell library. manufacturing.

419 views • 27 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Boolean Functions SOP Representation. Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003. Two-level logic (PLA). Multi-level logic (standard cells). Heuristic (espresso). Exact (QM). Boolean.

335 views • 20 slides

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems

ECE 667 Spring 2013 Synthesis and Verification of Digital Systems. Technology Mapping for FPGAs. D.Chen, J.Cong, DAOMap : A Depth optimal Area Optimization mapping algorithm for FPGA Designs, ICCAD 2004. Programming bit P. F = x 1 ’x 2 ’ + x 1 x 2. 2-Input LUT. x1 x2 F

294 views • 13 slides

ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits

ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits. Scheduling Algorithms Analytical approach - ILP. Scheduling – a Combinatorial Optimization Problem. NP-complete Problem Optimal solutions for special cases and ILP Integer linear program (ILP) Branch and bound

312 views • 21 slides

ECE 667 Spring 2007 Synthesis and Verification of Digital Circuits

ECE 667 Spring 2007 Synthesis and Verification of Digital Circuits. Design Implementation. Digital Circuit Implementation Approaches. Custom. Semicustom. Cell-based. Array-based. Standard Cells. Pre-diffused. Pre-wired. Ma. cro Cells. Compiled Cells. (Gate Arrays). (FPGA's).

331 views • 20 slides

ECE 667 Synthesis and Verification of Digital Systems

ECE 667 Synthesis and Verification of Digital Systems. Functional Decomposition. Slides adopted (with permission) from A. Mishchenko, 2003. Overview. The concept of functional decomposition Two uses of BDDs for decomposition as a computation engine to implement algorithms

251 views • 20 slides

More Related