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Low Power VMM for Telecom Designs

Low Power VMM for Telecom Designs. Paul Kaunds Kacper Technologies Pvt. Ltd. Contents. Introduction Power Aware Generation Base classes VMM_LP:: vmm_env VMM_LP:: vmm_lp_design VMM_LP::Framework VMM_LP:: vmm_lp_transition Power Aware Assertions Coverage Conclusion References  .

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Low Power VMM for Telecom Designs

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  1. Low Power VMMfor Telecom Designs Paul Kaunds Kacper Technologies Pvt. Ltd.

  2. Contents • Introduction • Power Aware Generation • Base classes • VMM_LP::vmm_env • VMM_LP::vmm_lp_design • VMM_LP::Framework • VMM_LP::vmm_lp_transition • Power Aware Assertions • Coverage • Conclusion • References  

  3. Introduction Power -key factor • Hand-held portable devices • Consumer electronics • Communications • Computing devices

  4. Introduction Low Power Design Techniques • Power Gating Shut down the power domains(parts) of the design when they are Inactive • Isolation Outputs from the shutdown domains into the active domains need to be maintained at predictable signal levels Power domain 2 Power domain 1 Isolationcells Power domain3

  5. Introduction Retention • During power off to sequential /memory elements • -current state stored is lost • Retention is a phenomenon that is used to restore • the states of sequential elements • Save -stores the state of the registers • Restore –restores the saved state back to registers Power domain (sequential element) Power domain (sequential element) restore save Retention Registers

  6. Introduction Power domain Power domain Retention Power domain F5 F5 FF FF FF FF save save save restore restore restore Retention Registers Retention Registers Retention Registers Register Register Register FF FF FF Register Register Register Register Register Register F5 F5 F5 FF FF FF Power domain x x x

  7. Introduction Level Shifter • In multi-voltage design, the signal connects to • logic at different voltage levels • Translates signal values from an input voltage swing to • a different output voltage swing (3v) VDD2 (1v) VDD1 • Level shifter cells are used for all the nets at the • voltage interface Power domain Power domain Level Shifter

  8. Introduction • Efficient Power management Power intent has to be reviewed at each phase along the design flow. We need a common format • Easy to use and understand • Can be declared independent of the RTL.

  9. Introduction UPF is an IEEE standard used to specify Low power Intent for Design implementation and Verification Top Design Testbench UPF Consistent power strategy is maintained from start to the end by having the same UPF file as reference.

  10. PowerVerification Challenges Advanced low power design techniques Power Gating, Multi Supply Multi Voltage (MSMV), Power-Retention, Power-Isolation etc Some of the low-power design verification challenges • Power switch off/on duration • Transitions between different power modes and states • Interface between power domains • Missing of level shifters, isolation and retention • Legal and illegal transitions • Clock enabling/toggling • Verifying retention registers and isolation cells • and level shifter Strategies

  11. VMM-LPFlow LP- DUT LP-DUT + TB (ALLON OK) TOOL MVRC VMM-LP Classes/Methods Static Verification Transitions/Sequences/Coverage/Random Test/RAL, Corner cases Rules & Guidelines Rules & Guidelines LP-DUT (Static OK) VCSLP/MVSIM TOOL LP-DUT (Complete) Dynamic Verification Rules & Guidelines

  12. VMM_LPFramework • Addressing the low power complex telecom design verification needs and challenges we made use of VMM-LP for NG-SONET/SDH verification. • VMM-LP classes adhere to SV based strategies, it helped us in Adopting and implementing power management verification. • VMM-LP provides a framework for accelerating the verification of low power designs.

  13. logic_pwr.sv Logical Scenario Generator Logical Interface Logicaldata Logical Driver Channel NG-SONET/SDH Back Plane Interface (DUT) Low power data Low Power Driver Low Power Interface Channel Power Scenario Power Management RAL VMM_LP Framework TOP

  14. Power Aware Generation • Developed a VMM based power generator • Enables the user to generate the power • control signals as • Random • Constrained random and • Directed • Designed with a creed that it can be hooked • into any VMM based environment. • User can generate the power signals without • any hassles in generating the complex power • control sequencing of signals.

  15. User Specific VMM Environment Generator Scoreboard Driver Monitor Power Aware Generation Power Generator • DUT Retention Registers, Isolation Cells and Level shifter strategy

  16. Power Aware Generation • Power scenario generation eased the verification • of power aware designs • Proved as a better solution for the generation • of power signals • User can simply enter values in the scenario • file depending on power specifications. • Verifies power management blocks and low • power strategies like Retention Registers, • Isolation Cells etc.

  17. Power Aware Generation • Following are the key features of our Scenario generation • Pursues standard power sequence specified in VMM_LP • All the power signals , power domains are parameterizable • Power Generator can be hooked to any VMM environment • Gives a well defined structure to define power sequences • Avoids overlapping of control signals • Allows multiple save, restore in each sequence

  18. Power Aware Generation clk save isolate Power control restore Inter_ seq_delay save width iso_on_power_off width iso_off_rst_on width save_iso_on_width pwr_off width restore_width iso_width pwr_on_iso_off width

  19. VMM_LP: Base Classes • VMM-LP inherits the legacy VMM base class libraries with newly added power aware constructs. • Power aware library ensures development of reusable and scalable verification infrastructure • VMM_LP base class library includes mainly • vmm_env • vmm_lp_design • vmm_lp_transition

  20. VMM_LP: Base Classes VMM NG-SONET/SDH Back Plane Interface (DUT) vmm_log vmm_data vmm_channel vmm_xactor vmm_env vmm_env :build( ) vmm_env :reset_dut( ) vmm_enmv:start()………. vmm_lp_transition vmm_lp_design vmm_env :hw_reset( ) vmm_env:power_on_reset( ) vmm_env:power_up( ) …… VMM_LP

  21. VMM_LP: vmm_env • hw_reset() • Assumes all the clocks and power signals are active vmm_lp ::vmm_env hw_reset( ); power_on_reset( ); reset_dut( ); power_up( ); cfg_dut( ) • power_on_reset () • Assumesall the clocks and power • signals are off • power_up () • Design can be maintained in a specific • initial power state or required active state • cfg_dut() • Brings design to a known configured state and • keeps ready to accept stimulus

  22. VMM_LP: vmm_env vmm_env:: reset_dut( ) vmm_env:: power_on_reset( ) All the clocks and power signals are off Automaticallycalls vmm_env:: hw_reset( ) All the clocks and power signals are active • Can be invoked repeatedly

  23. VMM_LP: vmm_lp_design • Mainly deals with power state management services • Helped us in keeping track of • current states • power modes • transitions

  24. VMM_LP: vmm_lp_design

  25. VMM_LP: vmm_lp_transition • vmm_lp_transition class is a virtual class that specifies how to transition a specific power domain from a specific power state to another power state • Gets the domain name being transitioned and state being transitioned from (source power state) and to(destination power state) • Checks if the state transition is complete

  26. Power Aware Assertions • Verification engineers have to concentrate on power bugs besides traditional functionality bugs. • VMM-LP came up with a well defined assertion rules and coverage techniques to achieve comprehensive low power verification. • Suggested some handy recommendations to ensure a consistent and portable implementation of the methodology

  27. Power Aware Assertions VMM_LP Environment NG-SONET/SDH Backplane Interface (DUT) Data Checkers Low Power Assertions Power Control Block Logic Control Block

  28. Power Aware Assertions PowerBugs

  29. Power Aware Assertions • Stepping towards efficient Low Power Telecom design • verification • Developed an automated Power Aware Assertion Library • Generic to any domain • Can be hooked to any design • Assertion library is built on the basis of VMM_LP rules • and guidelines with standard power sequencing Assertion Library

  30. Power Aware Assertions • General rules:Assertion to check that following control-signals never goto X/Z:- Isolation enable • - Save and restore signals • - Power gate/control signal • Assertions for Power State • - Assertion for each power state hit during simulation- Assertion for transition from a power state to another • power-state- Assertion for transition to illegal power-state- Assertion for transition from illegal power-state

  31. Power Aware Assertions • Rule3.6a:Clocks, resets and other high fanout nets of off islands must be gated inactive when the island is powered off • Rule 6.3a:Software addressable registers known to be in on/off islands must have assertions to verify that access happens only when they are in ON state • Rule 6.9:Assertions to guard against multiple rail changes at the same time must be present • Rule 3-4:Redundant activation of isolation-enable must be checked by appropriate assertions

  32. Power Aware Assertions - Example NMS/EMS Software addressable registers in on/off conditions Software Registers Software Registers Don’t access me

  33. Coverage • Coverage for each power state hit during • simulation • -Coverage for transition from a power state to • another power-state • -Coverage for transition to illegal power-state • -Coverage for transition from illegal power-state state1 state2 state2 state1 state3 legal transition Illegal transitions

  34. FutureWork Upf2vmmlp utility • Configurable utility • Reads an UPF file and generates the equivalent VMM- • LP SV code. • Generated code consists of VMM-LP configuration • classes that are extensions to the vmm_lp_design • and vmm_lp_transition classes. • Ensures that two representations are consistent • Users can bypass manual way of giving low • power data twice in its UPF and VMM-LP formats • Power State Manager (PSM) shall be • generated automatically.

  35. Conclusion • VMM LP is easier to adapt because of its systematic test flow and features like reusability and scalability • New Power aware Methodology approach in conjunction with VMM has proved effective at finding bugs in early stages of design. • Inherently friendly and helped us in creating random, directed and semi-random test cases • Provided us an insight into the assertions to check the correctness of the low power complex Telecom Designs • Facilitated for comprehensive power verification

  36. References • Verification Methodology Manual for SystemVerilog • Verification Methodology Manual for Low Power Other References • SrikanthJadcherla (Former group Director of Synopsys and CEO of SEER AKADEMI) • Janick Bergeron, Chris Spear and VikramMalik

  37. Questions

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