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Low Power designs in Memories

Low Power designs in Memories. Dr Elwin Chandra Monie. 4T & 6T SRAM cell Implementation. 4T Bistable Latch. __ BIT/BIT : Data line WORD : RD/WT. 6T Bistable Latch. Reading a Cell. I cell. D V = I cell * t ----- C b. Sense Amplifier. 1 -> 0. 0 -> 1. Writing a Cell.

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Low Power designs in Memories

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  1. Low Power designs in Memories Dr Elwin Chandra Monie

  2. 4T & 6T SRAM cell Implementation 4T Bistable Latch __ BIT/BIT : Data line WORD : RD/WT 6T Bistable Latch

  3. Reading a Cell Icell DV = Icell * t ----- Cb Sense Amplifier

  4. 1 -> 0 0 -> 1 Writing a Cell

  5. SRAM cell Precharge Column Decode

  6. SRAM, Putting it all together 2n rows, 2m * k columns n + m address lines, k bits data width

  7. SRAM Partitioning

  8. SRAM PartitioningDivided WordlineArchitecture

  9. Memory Subsystems Organization (1) • Two or more memory chips can be combined to create memory with more bits per location (two 8X2 chips can create a 8X4 memory)

  10. Memory Subsystems Organization (2) • Two or more memory chips can be combined to create more locations (two 8X2 chips can create 16X2 memory)

  11. Partioning summary • Partitioning reduces switched capacitance • Partioninginvolves a trade off between area, power and speed • For high speed designs, use short blocks(e.g 64 rows x 128 columns ) • Keep local bitline heights small • For low power designs use tall narrow blocks (e.g 256 rows x 64 columns) • Keep the number of columns same as the access width to minimize wasted power

  12. Pulsed Word Line • Pulsed WORD line to limit the duration of reading so that the BIT line has lesser swing

  13. Pulsed Word Line

  14. Bit Line Isolation • Main idea: Isolate sense amplifiers from bit line after sensing, to prevent from having large voltage swings

  15. Pulsed sense amplifier

  16. Reducing power in decode circuit Two stage decoder

  17. V DD V V PC DD DD y x x BL BL EQ SE WL i (b) Doubled-ended Current Mirror Amplifier V DD SRAM cell i y y Diff. Sense x x x x Amp y y SE D D Differential Sensing - SRAM M3 M4 M1 M2 M5 (a) SRAM sensing scheme. (c) Cross-Coupled Amplifier

  18. Latch-Based Sense Amplifier

  19. Static Pull-up Precharge Clocked Precharge clock BL !BL BL !BL equalization transistor - speeds up equalization of the two bit lines by allowing the capacitance and pull-up device of the nondischarged bit line to assist in precharging the discharged line Bit Line Precharging

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