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More Sequential Circuits

More Sequential Circuits. Class 23-More Sequential Circuits. An up/down counter A loadable down counter with signal Material from section 5-5 of text. Design of and up/down counter.

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More Sequential Circuits

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  1. More Sequential Circuits Copyright 2009 - Joanne DeGroat, ECE, OSU

  2. Class 23-More Sequential Circuits • An up/down counter • A loadable down counter with signal • Material from section 5-5 of text Copyright 2009 - Joanne DeGroat, ECE, OSU

  3. Design of and up/down counter • Problem Statement: Design a 3 bit binary clocked counter that counts up when the input C = 1 and counts down when the input C = 0. When the counter gets to 111 (000) it rolls over to 000 (111). Copyright 2009 - Joanne DeGroat, ECE, OSU

  4. Problem Formulation • Will use a state table for this problem • C=0 down C=1 up • Present State Next State Next State • 000 111 001 • 001 000 010 • 010 001 011 • 011 010 100 • 100 011 101 • 101 100 110 • 110 101 111 • 111 110 000 Copyright 2009 - Joanne DeGroat, ECE, OSU

  5. State Assignment • As this design involves a counter it already has binary values assigned to the states. • So we can move straight to creation of the next state generation. • The system will use D Flip-flops. Copyright 2009 - Joanne DeGroat, ECE, OSU

  6. Next State Generation • In the table the Present State will be denoted by the 3-bit binary value as seen in the state table. The binary value is Q2Q1Q0. • First the generation of Q0. Copyright 2009 - Joanne DeGroat, ECE, OSU

  7. Next State Generation D1 • Generate the next state equation for D1 Copyright 2009 - Joanne DeGroat, ECE, OSU

  8. Next State Generation D2 • Generate the next state equation for D2 Copyright 2009 - Joanne DeGroat, ECE, OSU

  9. Output Generation • Output generation is easy as it just the current state. Copyright 2009 - Joanne DeGroat, ECE, OSU

  10. Verification via HDL • The models Copyright 2009 - Joanne DeGroat, ECE, OSU

  11. The counter model • Uses the D FF Copyright 2009 - Joanne DeGroat, ECE, OSU

  12. The Testbench • Need to apply stimulus and look at results. Copyright 2009 - Joanne DeGroat, ECE, OSU

  13. Simultion Results • The waveform for counting up Copyright 2009 - Joanne DeGroat, ECE, OSU

  14. Simultion Results • The waveform for counting down Copyright 2009 - Joanne DeGroat, ECE, OSU

  15. Simulation Results • Waveform for up again and back to down Copyright 2009 - Joanne DeGroat, ECE, OSU

  16. Changing format to octal display • For a more readable output Copyright 2009 - Joanne DeGroat, ECE, OSU

  17. A Loadable countdown timer • Specification: Design a loadable 3-bit countdown timer the after loading counts down to 0 and then generates a signal Z which will stay asserted as long as the countdown is enabled. • When the counter reaches 0 it remains there until a new count is loaded. Copyright 2009 - Joanne DeGroat, ECE, OSU

  18. The state table • The state table showing both count enable and load Copyright 2009 - Joanne DeGroat, ECE, OSU

  19. K-maps • The K-maps for the circuit are. Copyright 2009 - Joanne DeGroat, ECE, OSU

  20. The output • The output signal Z is asserted when state 000 is reached. It stays asserted as long as C is asserted. Copyright 2009 - Joanne DeGroat, ECE, OSU

  21. The circuit • Has 3 FFs Copyright 2009 - Joanne DeGroat, ECE, OSU

  22. Class 23 assignment • Covered sections 5-5 • Problems for hand in • Nothing new • Problems for practice • Nothing new • Reading for next class: 5-6 Copyright 2009 - Joanne DeGroat, ECE, OSU

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