Data Concentrator Board Implementation Concept Rev 2 Update

1. Data Concentrator Board Implementation ConceptRev 2 Update Tom O’Bannon University of Maryland 7/16/2013

2. Objectives • These charts are not intended to imply any decisions. • The goal here is to stimulate some dialog: • Ensure understanding of key requirements • Offer some general conceptual talking points of the UT electronics implementation details

3. Physical Environment for Data Concentrator Electronics1 1 Per ‘Mechanical Requirements Document for the LHCb UT Upgrade Tracker” Rev 5/3/2013 • Ambient temperature: 20 ± 2°C • Ambient pressure: Normal Atmospheric • Ambient relative humidity: 40% (typ) • Radiation (10-year exposure): 10 to 20 Krad • Does this include a safety factor?

4. UT DCB Locations Station 1, Layer B, Upper Station 1, Layer A, Upper Station 0, Layer B, Upper Station 0, Layer A, Upper UT Detector is electrically divided between top and bottom Upper Station 1, Layer B, Lower Station 1, Layer A, Lower Lower Station 0, Layer B, Lower Station 0, Layer A, Lower UT Detector is split apart Left-from-right for maintenance access Physical Configuration: 8 Edge Interfaces x2 for Flex Tails to Data Concentrator Boards (x2 facilitates mechanical right-left separation)

5. UT ASIC Access via Flextails1:Station 0: UTaX and UTaU Station 0, Layer B, Upper= 496 Station 0, Layer A, Upper= 496 Station 0 has 1984 FE ASICs Station 0, Layer B, Lower= 496 Station 0, Layer A, Lower= 496 1 This analysis based upon JC Wang presentation on 6/17/13

6. UT ASIC Access via Flextails1:Station 1: UTbXand UTbU Station 1, Layer B, Upper= 552 Station 1, Layer A, Upper= 552 Station 1 has 2208 FE ASICs Station 1, Layer B, Lower= 552 Station 1, Layer A, Lower= 552 1 This analysis based upon JC Wang presentation on 6/17/13

7. UT ASIC E-Link Distribution1:Station 0: UTaX and UTaU Station 0 has 2754 E-Links Per Quadrant via 8 Flex Tails:  56 Hybrids  ~ 350 E-Links 1 This analysis based upon JC Wang presentation on 6/17/13

8. UT ASIC E-Link Distribution1:Station 1: UTbVand UTbX Station 1 has 3254 E-Links Per Quadrant via 9 Flex Tails:  63 Hybrids  ~ 410 E-Links 1 This analysis based upon JC Wang presentation on 6/17/13

9. UT Data Interface Summary Station 0 Per Quadrant via 8 Flex Tails:  56 Hybrids  ~ 345 E-Links  ~ 35 GBTx’s 1984 FE ASICs 2754 E-Links 276 GBTx’s Station 1 Per Quadrant via 9 Flex Tails:  63 Hybrids  ~ 407 E-Links  ~ 41 GBTx’s 2208 FE ASICs 3254 E-Links 326 GBTx’s UT Total Raw Data Rate1  1,945.6 Gbps 4,192 FE ASICs 952 Hybrids 6,008 E-Links 608 GBTx’s 1 ( ie without data link overhead)

10. Initial Electronics Concept-Annotated GBTX-Master DCB DC-DC Power Backplane

11. Board-Level System Partition Options 1 Note--System board-level partitioning will increase this quantity slightly • Assume standard EDAC (80 bits/frame) for GBTx operation • Total of 6008 Data E-Links (initial estimate only) • Requires 601 GBTx’s1dedicated for data transmission • Example Partitions: • 12 GBTXs per board requires 51 DCBs • 8 GBTXs per board requires 75 DCBs • What are the mechanical interface options along the left and right of the topand bottom detector plane edges? • Option: one backplane per detector plane quadrant • Yields 16 smaller backplanes • Facilitates right-left mechanical split • Would be helpful if the 4 quadrants of each detector plane are made symmetrical

12. Some More Questions • Health and status sensors? • Type, quantity, update rates • Failsafes and interlock approach? • FE ASIC control interfaces via GBT-SCA: • Interface port type? • I2C, JTAG, parallel port, SPI • Data update rates? • Number of FE ASICs per GBT-SCA? • Initial prototype effort/support? • DC-DC power distribution and regulation • FE ASICS • DCBs • Control Board • Test Equipment plan? • Any dedicated handshake signal interfaces required between FE ASICs and GBTs? • Data Valid / txRdy / rx_Rdy

13. Digital Control Interface Signal Details/Options • GBT-SCA—Control via one 80 Mbps E-Port • SPI (Serial Peripheral Interface) • Serial Clock • Serial Data out • Serial Data in • 1 select line per slave • I2C (Inter-Integrated Circuit) • Serial clock • Serial Data (bidir) • Signals are open drain to allow multiple bus masters • JTAG • Memory interface • Parallel Port • Interrupts • GBTx (Master)– 32 ports available at 80 Mbps • Is this a potential FE ASIC control interface? • E-Ports (AKA E-Links) • Data In (to GBTx) • Data Out (from GBTx) • Clock Out (from GBTx)

14. GBT-SCA Analog Interface Signal Details1 1 Per Dec 15, 2011 Kostas.Kloukinas@cern.chsummary charts • 12-bit ADC • Input range: GND < Vin < 1 V • Max. conversion rate ≈ 3.5 KHz • 32 Multiplexed Input channels • 31 general user input channels • 1 channel dedicated to on-chip temperature sensor

15. DCBFE ASIC Interconnect Concept…

16. DC Power Conversion, Regulation, and Filtering Split the FE ASIC and DCBs DC power rails • What are the preferred distributed DC power rail voltages • Input = 9V (11.5V at counting room)? • Backplane rails: ____? • GBTx=1.5V, FE ASIC= ___?, VL= 2.5V • Select a standard (ie w/ CERN Heritage) rad-tolerant LDO to facilitate local power regulation and switching noise filtering

17. An Alternate ‘Back Burner’ Approach Above excerpt from CMS ngCCM(Terry Shaw) Potentially useful in the initial prototype detector slice proof-of-concept build • Alternate prototype approach using intermediate FPGAs between FE ASICs and GBTx. • Flexibility since it can be remotely re-programmed • Potential GBT SERDES alternate via SF2 SOC effort if GBTs not readily available • Potential to reduce risks by accommodating unexpected ‘design features’ between FE ASICs and GBTs

18. Near Term Path Forward • Discuss support needs for prototype development • Continue system partition efforts • Signal tabulations at all interfaces • Power rollups • Estimate board areas • Define mechanical interfaces